utility.hh revision 5569
12440SN/A/* 22440SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32440SN/A * All rights reserved. 42440SN/A * 52440SN/A * Redistribution and use in source and binary forms, with or without 62440SN/A * modification, are permitted provided that the following conditions are 72440SN/A * met: redistributions of source code must retain the above copyright 82440SN/A * notice, this list of conditions and the following disclaimer; 92440SN/A * redistributions in binary form must reproduce the above copyright 102440SN/A * notice, this list of conditions and the following disclaimer in the 112440SN/A * documentation and/or other materials provided with the distribution; 122440SN/A * neither the name of the copyright holders nor the names of its 132440SN/A * contributors may be used to endorse or promote products derived from 142440SN/A * this software without specific prior written permission. 152440SN/A * 162440SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172440SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182440SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192440SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202440SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212440SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222440SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232440SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242440SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252440SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262440SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302440SN/A */ 312440SN/A 322440SN/A#ifndef __ARCH_ALPHA_UTILITY_HH__ 332440SN/A#define __ARCH_ALPHA_UTILITY_HH__ 342440SN/A 352440SN/A#include "arch/alpha/types.hh" 362972Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 372460SN/A#include "arch/alpha/regfile.hh" 382440SN/A#include "base/misc.hh" 395569Snate@binkert.org#include "config/full_system.hh" 403120Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 412440SN/A 425569Snate@binkert.orgnamespace AlphaISA { 435569Snate@binkert.org 445569Snate@binkert.orguint64_t getArgument(ThreadContext *tc, int number, bool fp); 455569Snate@binkert.org 465569Snate@binkert.orginline bool 475569Snate@binkert.orginUserMode(ThreadContext *tc) 482440SN/A{ 495569Snate@binkert.org return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; 505569Snate@binkert.org} 514826Ssaidi@eecs.umich.edu 525569Snate@binkert.orginline bool 535569Snate@binkert.orgisCallerSaveIntegerRegister(unsigned int reg) 545569Snate@binkert.org{ 555569Snate@binkert.org panic("register classification not implemented"); 565569Snate@binkert.org return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 575569Snate@binkert.org} 583577Sgblack@eecs.umich.edu 595569Snate@binkert.orginline bool 605569Snate@binkert.orgisCalleeSaveIntegerRegister(unsigned int reg) 615569Snate@binkert.org{ 625569Snate@binkert.org panic("register classification not implemented"); 635569Snate@binkert.org return (reg >= 9 && reg <= 15); 645569Snate@binkert.org} 652440SN/A 665569Snate@binkert.orginline bool 675569Snate@binkert.orgisCallerSaveFloatRegister(unsigned int reg) 685569Snate@binkert.org{ 695569Snate@binkert.org panic("register classification not implemented"); 705569Snate@binkert.org return false; 715569Snate@binkert.org} 722440SN/A 735569Snate@binkert.orginline bool 745569Snate@binkert.orgisCalleeSaveFloatRegister(unsigned int reg) 755569Snate@binkert.org{ 765569Snate@binkert.org panic("register classification not implemented"); 775569Snate@binkert.org return false; 785569Snate@binkert.org} 792440SN/A 805569Snate@binkert.orginline Addr 815569Snate@binkert.orgalignAddress(const Addr &addr, unsigned int nbytes) 825569Snate@binkert.org{ 835569Snate@binkert.org return (addr & ~(nbytes - 1)); 845569Snate@binkert.org} 852440SN/A 865569Snate@binkert.org// Instruction address compression hooks 875569Snate@binkert.orginline Addr 885569Snate@binkert.orgrealPCToFetchPC(const Addr &addr) 895569Snate@binkert.org{ 905569Snate@binkert.org return addr; 915569Snate@binkert.org} 922440SN/A 935569Snate@binkert.orginline Addr 945569Snate@binkert.orgfetchPCToRealPC(const Addr &addr) 955569Snate@binkert.org{ 965569Snate@binkert.org return addr; 975569Snate@binkert.org} 982440SN/A 995569Snate@binkert.org// the size of "fetched" instructions (not necessarily the size 1005569Snate@binkert.org// of real instructions for PISA) 1015569Snate@binkert.orginline size_t 1025569Snate@binkert.orgfetchInstSize() 1035569Snate@binkert.org{ 1045569Snate@binkert.org return sizeof(MachInst); 1055569Snate@binkert.org} 1062440SN/A 1075569Snate@binkert.orginline MachInst 1085569Snate@binkert.orgmakeRegisterCopy(int dest, int src) 1095569Snate@binkert.org{ 1105569Snate@binkert.org panic("makeRegisterCopy not implemented"); 1115569Snate@binkert.org return 0; 1125569Snate@binkert.org} 1132440SN/A 1145569Snate@binkert.org// Machine operations 1155569Snate@binkert.orgvoid saveMachineReg(AnyReg &savereg, const RegFile ®_file, int regnum); 1165569Snate@binkert.orgvoid restoreMachineReg(RegFile ®s, const AnyReg ®, int regnum); 1172440SN/A 1185569Snate@binkert.org/** 1195569Snate@binkert.org * Function to insure ISA semantics about 0 registers. 1205569Snate@binkert.org * @param tc The thread context. 1215569Snate@binkert.org */ 1225569Snate@binkert.orgtemplate <class TC> 1235569Snate@binkert.orgvoid zeroRegisters(TC *tc); 1242440SN/A 1255569Snate@binkert.org// Alpha IPR register accessors 1265569Snate@binkert.orginline bool PcPAL(Addr addr) { return addr & 0x3; } 1275569Snate@binkert.orginline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); } 1282440SN/A 1295569Snate@binkert.org//////////////////////////////////////////////////////////////////////// 1305569Snate@binkert.org// 1315569Snate@binkert.org// Translation stuff 1325569Snate@binkert.org// 1332440SN/A 1345569Snate@binkert.orginline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 1352440SN/A 1365569Snate@binkert.org// User Virtual 1375569Snate@binkert.orginline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 1382440SN/A 1395569Snate@binkert.org// Kernel Direct Mapped 1405569Snate@binkert.orginline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 1415569Snate@binkert.orginline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 1422440SN/A 1435569Snate@binkert.org// Kernel Virtual 1445569Snate@binkert.orginline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 1452440SN/A 1465569Snate@binkert.orginline Addr 1475569Snate@binkert.orgTruncPage(Addr addr) 1485569Snate@binkert.org{ return addr & ~(PageBytes - 1); } 1492440SN/A 1505569Snate@binkert.orginline Addr 1515569Snate@binkert.orgRoundPage(Addr addr) 1525569Snate@binkert.org{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } 1532440SN/A 1545569Snate@binkert.orgvoid initIPRs(ThreadContext *tc, int cpuId); 1555569Snate@binkert.org#if FULL_SYSTEM 1565569Snate@binkert.orgvoid initCPU(ThreadContext *tc, int cpuId); 1572440SN/A 1585569Snate@binkert.org/** 1595569Snate@binkert.org * Function to check for and process any interrupts. 1605569Snate@binkert.org * @param tc The thread context. 1615569Snate@binkert.org */ 1625569Snate@binkert.orgtemplate <class TC> 1635569Snate@binkert.orgvoid processInterrupts(TC *tc); 1642440SN/A#endif 1652440SN/A 1662440SN/A} // namespace AlphaISA 1672440SN/A 1685569Snate@binkert.org#endif // __ARCH_ALPHA_UTILITY_HH__ 169