utility.hh revision 4826
17732SAli.Saidi@ARM.com/*
27732SAli.Saidi@ARM.com * Copyright (c) 2003-2005 The Regents of The University of Michigan
37732SAli.Saidi@ARM.com * All rights reserved.
47732SAli.Saidi@ARM.com *
57732SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without
67732SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are
77732SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright
87732SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer;
97732SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright
107732SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the
117732SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution;
127732SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its
137732SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from
147732SAli.Saidi@ARM.com * this software without specific prior written permission.
157732SAli.Saidi@ARM.com *
167732SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
177732SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
187732SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
197732SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
207732SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
217732SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
227732SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
237732SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
247732SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
257732SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
267732SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
277732SAli.Saidi@ARM.com *
287732SAli.Saidi@ARM.com * Authors: Nathan Binkert
297732SAli.Saidi@ARM.com *          Steve Reinhardt
307732SAli.Saidi@ARM.com */
317732SAli.Saidi@ARM.com
327732SAli.Saidi@ARM.com#ifndef __ARCH_ALPHA_UTILITY_HH__
337732SAli.Saidi@ARM.com#define __ARCH_ALPHA_UTILITY_HH__
347732SAli.Saidi@ARM.com
357732SAli.Saidi@ARM.com#include "config/full_system.hh"
367732SAli.Saidi@ARM.com#include "arch/alpha/types.hh"
377732SAli.Saidi@ARM.com#include "arch/alpha/isa_traits.hh"
387732SAli.Saidi@ARM.com#include "arch/alpha/regfile.hh"
397732SAli.Saidi@ARM.com#include "base/misc.hh"
407732SAli.Saidi@ARM.com#include "cpu/thread_context.hh"
417732SAli.Saidi@ARM.com
427732SAli.Saidi@ARM.comnamespace AlphaISA
439660SAndreas.Sandberg@ARM.com{
447732SAli.Saidi@ARM.com
458987SAli.Saidi@ARM.com    uint64_t getArgument(ThreadContext *tc, int number, bool fp);
468987SAli.Saidi@ARM.com
478987SAli.Saidi@ARM.com    static inline bool
488987SAli.Saidi@ARM.com    inUserMode(ThreadContext *tc)
497732SAli.Saidi@ARM.com    {
507732SAli.Saidi@ARM.com        return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
517732SAli.Saidi@ARM.com    }
527732SAli.Saidi@ARM.com
537732SAli.Saidi@ARM.com    inline bool isCallerSaveIntegerRegister(unsigned int reg) {
549660SAndreas.Sandberg@ARM.com        panic("register classification not implemented");
559686Sandreas@sandberg.pp.se        return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
569660SAndreas.Sandberg@ARM.com    }
579660SAndreas.Sandberg@ARM.com
589660SAndreas.Sandberg@ARM.com    inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
599660SAndreas.Sandberg@ARM.com        panic("register classification not implemented");
609660SAndreas.Sandberg@ARM.com        return (reg >= 9 && reg <= 15);
619660SAndreas.Sandberg@ARM.com    }
629660SAndreas.Sandberg@ARM.com
639686Sandreas@sandberg.pp.se    inline bool isCallerSaveFloatRegister(unsigned int reg) {
649686Sandreas@sandberg.pp.se        panic("register classification not implemented");
659686Sandreas@sandberg.pp.se        return false;
669686Sandreas@sandberg.pp.se    }
679686Sandreas@sandberg.pp.se
689660SAndreas.Sandberg@ARM.com    inline bool isCalleeSaveFloatRegister(unsigned int reg) {
699660SAndreas.Sandberg@ARM.com        panic("register classification not implemented");
709660SAndreas.Sandberg@ARM.com        return false;
717732SAli.Saidi@ARM.com    }
729660SAndreas.Sandberg@ARM.com
739660SAndreas.Sandberg@ARM.com    inline Addr alignAddress(const Addr &addr,
749660SAndreas.Sandberg@ARM.com                                         unsigned int nbytes) {
759660SAndreas.Sandberg@ARM.com        return (addr & ~(nbytes - 1));
769660SAndreas.Sandberg@ARM.com    }
779660SAndreas.Sandberg@ARM.com
789686Sandreas@sandberg.pp.se    // Instruction address compression hooks
799660SAndreas.Sandberg@ARM.com    inline Addr realPCToFetchPC(const Addr &addr) {
809660SAndreas.Sandberg@ARM.com        return addr;
819660SAndreas.Sandberg@ARM.com    }
827732SAli.Saidi@ARM.com
839660SAndreas.Sandberg@ARM.com    inline Addr fetchPCToRealPC(const Addr &addr) {
849660SAndreas.Sandberg@ARM.com        return addr;
859660SAndreas.Sandberg@ARM.com    }
869660SAndreas.Sandberg@ARM.com
879660SAndreas.Sandberg@ARM.com    // the size of "fetched" instructions (not necessarily the size
889660SAndreas.Sandberg@ARM.com    // of real instructions for PISA)
899660SAndreas.Sandberg@ARM.com    inline size_t fetchInstSize() {
909660SAndreas.Sandberg@ARM.com        return sizeof(MachInst);
919660SAndreas.Sandberg@ARM.com    }
929660SAndreas.Sandberg@ARM.com
939660SAndreas.Sandberg@ARM.com    inline MachInst makeRegisterCopy(int dest, int src) {
949660SAndreas.Sandberg@ARM.com        panic("makeRegisterCopy not implemented");
959660SAndreas.Sandberg@ARM.com        return 0;
969660SAndreas.Sandberg@ARM.com    }
979660SAndreas.Sandberg@ARM.com
989660SAndreas.Sandberg@ARM.com    // Machine operations
999660SAndreas.Sandberg@ARM.com
1009660SAndreas.Sandberg@ARM.com    void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
1019660SAndreas.Sandberg@ARM.com                               int regnum);
1029660SAndreas.Sandberg@ARM.com
1039660SAndreas.Sandberg@ARM.com    void restoreMachineReg(RegFile &regs, const AnyReg &reg,
1049660SAndreas.Sandberg@ARM.com                                  int regnum);
1059660SAndreas.Sandberg@ARM.com
1069660SAndreas.Sandberg@ARM.com    /**
1079660SAndreas.Sandberg@ARM.com     * Function to insure ISA semantics about 0 registers.
1089660SAndreas.Sandberg@ARM.com     * @param tc The thread context.
1099660SAndreas.Sandberg@ARM.com     */
1109660SAndreas.Sandberg@ARM.com    template <class TC>
1119660SAndreas.Sandberg@ARM.com    void zeroRegisters(TC *tc);
1129660SAndreas.Sandberg@ARM.com
1139660SAndreas.Sandberg@ARM.com    // Alpha IPR register accessors
1149660SAndreas.Sandberg@ARM.com    inline bool PcPAL(Addr addr) { return addr & 0x3; }
1159660SAndreas.Sandberg@ARM.com    inline void startupCPU(ThreadContext *tc, int cpuId) {
1169660SAndreas.Sandberg@ARM.com        tc->activate(0);
1179660SAndreas.Sandberg@ARM.com    }
1189660SAndreas.Sandberg@ARM.com#if FULL_SYSTEM
1199660SAndreas.Sandberg@ARM.com
1209660SAndreas.Sandberg@ARM.com    ////////////////////////////////////////////////////////////////////////
1219660SAndreas.Sandberg@ARM.com    //
1229660SAndreas.Sandberg@ARM.com    //  Translation stuff
1239660SAndreas.Sandberg@ARM.com    //
124
125    inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
126
127    // User Virtual
128    inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
129
130    // Kernel Direct Mapped
131    inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
132    inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
133
134    // Kernel Virtual
135    inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
136
137    inline Addr
138    TruncPage(Addr addr)
139    { return addr & ~(PageBytes - 1); }
140
141    inline Addr
142    RoundPage(Addr addr)
143    { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
144
145    void initCPU(ThreadContext *tc, int cpuId);
146    void initIPRs(ThreadContext *tc, int cpuId);
147
148    /**
149     * Function to check for and process any interrupts.
150     * @param tc The thread context.
151     */
152    template <class TC>
153    void processInterrupts(TC *tc);
154#endif
155
156} // namespace AlphaISA
157
158#endif
159