utility.hh revision 4826
12440SN/A/* 22440SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32440SN/A * All rights reserved. 42440SN/A * 52440SN/A * Redistribution and use in source and binary forms, with or without 62440SN/A * modification, are permitted provided that the following conditions are 72440SN/A * met: redistributions of source code must retain the above copyright 82440SN/A * notice, this list of conditions and the following disclaimer; 92440SN/A * redistributions in binary form must reproduce the above copyright 102440SN/A * notice, this list of conditions and the following disclaimer in the 112440SN/A * documentation and/or other materials provided with the distribution; 122440SN/A * neither the name of the copyright holders nor the names of its 132440SN/A * contributors may be used to endorse or promote products derived from 142440SN/A * this software without specific prior written permission. 152440SN/A * 162440SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172440SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182440SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192440SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202440SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212440SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222440SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232440SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242440SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252440SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262440SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302440SN/A */ 312440SN/A 322440SN/A#ifndef __ARCH_ALPHA_UTILITY_HH__ 332440SN/A#define __ARCH_ALPHA_UTILITY_HH__ 342440SN/A 352440SN/A#include "config/full_system.hh" 362440SN/A#include "arch/alpha/types.hh" 372972Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 382460SN/A#include "arch/alpha/regfile.hh" 392440SN/A#include "base/misc.hh" 403120Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 412440SN/A 422440SN/Anamespace AlphaISA 432440SN/A{ 442440SN/A 454826Ssaidi@eecs.umich.edu uint64_t getArgument(ThreadContext *tc, int number, bool fp); 464826Ssaidi@eecs.umich.edu 473577Sgblack@eecs.umich.edu static inline bool 483577Sgblack@eecs.umich.edu inUserMode(ThreadContext *tc) 493577Sgblack@eecs.umich.edu { 504172Ssaidi@eecs.umich.edu return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 513577Sgblack@eecs.umich.edu } 523577Sgblack@eecs.umich.edu 532467SN/A inline bool isCallerSaveIntegerRegister(unsigned int reg) { 542440SN/A panic("register classification not implemented"); 552440SN/A return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 562440SN/A } 572440SN/A 582467SN/A inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 592440SN/A panic("register classification not implemented"); 602440SN/A return (reg >= 9 && reg <= 15); 612440SN/A } 622440SN/A 632467SN/A inline bool isCallerSaveFloatRegister(unsigned int reg) { 642440SN/A panic("register classification not implemented"); 652440SN/A return false; 662440SN/A } 672440SN/A 682467SN/A inline bool isCalleeSaveFloatRegister(unsigned int reg) { 692440SN/A panic("register classification not implemented"); 702440SN/A return false; 712440SN/A } 722440SN/A 732467SN/A inline Addr alignAddress(const Addr &addr, 742440SN/A unsigned int nbytes) { 752440SN/A return (addr & ~(nbytes - 1)); 762440SN/A } 772440SN/A 782440SN/A // Instruction address compression hooks 792467SN/A inline Addr realPCToFetchPC(const Addr &addr) { 802440SN/A return addr; 812440SN/A } 822440SN/A 832467SN/A inline Addr fetchPCToRealPC(const Addr &addr) { 842440SN/A return addr; 852440SN/A } 862440SN/A 872440SN/A // the size of "fetched" instructions (not necessarily the size 882440SN/A // of real instructions for PISA) 892467SN/A inline size_t fetchInstSize() { 902440SN/A return sizeof(MachInst); 912440SN/A } 922440SN/A 932467SN/A inline MachInst makeRegisterCopy(int dest, int src) { 942440SN/A panic("makeRegisterCopy not implemented"); 952440SN/A return 0; 962440SN/A } 972440SN/A 982440SN/A // Machine operations 992440SN/A 1002440SN/A void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 1012440SN/A int regnum); 1022440SN/A 1032440SN/A void restoreMachineReg(RegFile ®s, const AnyReg ®, 1042440SN/A int regnum); 1052440SN/A 1062440SN/A /** 1072440SN/A * Function to insure ISA semantics about 0 registers. 1082680Sktlim@umich.edu * @param tc The thread context. 1092440SN/A */ 1102680Sktlim@umich.edu template <class TC> 1112680Sktlim@umich.edu void zeroRegisters(TC *tc); 1122440SN/A 1133961Sgblack@eecs.umich.edu // Alpha IPR register accessors 1143961Sgblack@eecs.umich.edu inline bool PcPAL(Addr addr) { return addr & 0x3; } 1154194Ssaidi@eecs.umich.edu inline void startupCPU(ThreadContext *tc, int cpuId) { 1164194Ssaidi@eecs.umich.edu tc->activate(0); 1174194Ssaidi@eecs.umich.edu } 1182440SN/A#if FULL_SYSTEM 1192440SN/A 1202440SN/A //////////////////////////////////////////////////////////////////////// 1212440SN/A // 1222440SN/A // Translation stuff 1232440SN/A // 1242440SN/A 1252467SN/A inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 1262440SN/A 1272440SN/A // User Virtual 1282467SN/A inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 1292440SN/A 1302440SN/A // Kernel Direct Mapped 1312467SN/A inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 1322467SN/A inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 1332440SN/A 1342440SN/A // Kernel Virtual 1352467SN/A inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 1362440SN/A 1372467SN/A inline Addr 1382440SN/A TruncPage(Addr addr) 1392440SN/A { return addr & ~(PageBytes - 1); } 1402440SN/A 1412467SN/A inline Addr 1422440SN/A RoundPage(Addr addr) 1432440SN/A { return (addr + PageBytes - 1) & ~(PageBytes - 1); } 1442440SN/A 1452680Sktlim@umich.edu void initCPU(ThreadContext *tc, int cpuId); 1462680Sktlim@umich.edu void initIPRs(ThreadContext *tc, int cpuId); 1472440SN/A 1482440SN/A /** 1492440SN/A * Function to check for and process any interrupts. 1502680Sktlim@umich.edu * @param tc The thread context. 1512440SN/A */ 1522680Sktlim@umich.edu template <class TC> 1532680Sktlim@umich.edu void processInterrupts(TC *tc); 1542440SN/A#endif 1552440SN/A 1562440SN/A} // namespace AlphaISA 1572440SN/A 1582440SN/A#endif 159