utility.hh revision 4194
12440SN/A/* 22440SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32440SN/A * All rights reserved. 42440SN/A * 52440SN/A * Redistribution and use in source and binary forms, with or without 62440SN/A * modification, are permitted provided that the following conditions are 72440SN/A * met: redistributions of source code must retain the above copyright 82440SN/A * notice, this list of conditions and the following disclaimer; 92440SN/A * redistributions in binary form must reproduce the above copyright 102440SN/A * notice, this list of conditions and the following disclaimer in the 112440SN/A * documentation and/or other materials provided with the distribution; 122440SN/A * neither the name of the copyright holders nor the names of its 132440SN/A * contributors may be used to endorse or promote products derived from 142440SN/A * this software without specific prior written permission. 152440SN/A * 162440SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172440SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182440SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192440SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202440SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212440SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222440SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232440SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242440SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252440SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262440SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302440SN/A */ 312440SN/A 322440SN/A#ifndef __ARCH_ALPHA_UTILITY_HH__ 332440SN/A#define __ARCH_ALPHA_UTILITY_HH__ 342440SN/A 352440SN/A#include "config/full_system.hh" 362440SN/A#include "arch/alpha/types.hh" 372972Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 382460SN/A#include "arch/alpha/regfile.hh" 392440SN/A#include "base/misc.hh" 403120Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 412440SN/A 422440SN/Anamespace AlphaISA 432440SN/A{ 442440SN/A 453577Sgblack@eecs.umich.edu static inline bool 463577Sgblack@eecs.umich.edu inUserMode(ThreadContext *tc) 473577Sgblack@eecs.umich.edu { 484172Ssaidi@eecs.umich.edu return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 493577Sgblack@eecs.umich.edu } 503577Sgblack@eecs.umich.edu 512440SN/A static inline ExtMachInst 523484Sktlim@umich.edu makeExtMI(MachInst inst, Addr pc) { 532440SN/A#if FULL_SYSTEM 542440SN/A ExtMachInst ext_inst = inst; 553484Sktlim@umich.edu if (pc && 0x1) 563484Sktlim@umich.edu return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); 572440SN/A else 582440SN/A return ext_inst; 592440SN/A#else 602440SN/A return ExtMachInst(inst); 612440SN/A#endif 622440SN/A } 632440SN/A 642467SN/A inline bool isCallerSaveIntegerRegister(unsigned int reg) { 652440SN/A panic("register classification not implemented"); 662440SN/A return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 672440SN/A } 682440SN/A 692467SN/A inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 702440SN/A panic("register classification not implemented"); 712440SN/A return (reg >= 9 && reg <= 15); 722440SN/A } 732440SN/A 742467SN/A inline bool isCallerSaveFloatRegister(unsigned int reg) { 752440SN/A panic("register classification not implemented"); 762440SN/A return false; 772440SN/A } 782440SN/A 792467SN/A inline bool isCalleeSaveFloatRegister(unsigned int reg) { 802440SN/A panic("register classification not implemented"); 812440SN/A return false; 822440SN/A } 832440SN/A 842467SN/A inline Addr alignAddress(const Addr &addr, 852440SN/A unsigned int nbytes) { 862440SN/A return (addr & ~(nbytes - 1)); 872440SN/A } 882440SN/A 892440SN/A // Instruction address compression hooks 902467SN/A inline Addr realPCToFetchPC(const Addr &addr) { 912440SN/A return addr; 922440SN/A } 932440SN/A 942467SN/A inline Addr fetchPCToRealPC(const Addr &addr) { 952440SN/A return addr; 962440SN/A } 972440SN/A 982440SN/A // the size of "fetched" instructions (not necessarily the size 992440SN/A // of real instructions for PISA) 1002467SN/A inline size_t fetchInstSize() { 1012440SN/A return sizeof(MachInst); 1022440SN/A } 1032440SN/A 1042467SN/A inline MachInst makeRegisterCopy(int dest, int src) { 1052440SN/A panic("makeRegisterCopy not implemented"); 1062440SN/A return 0; 1072440SN/A } 1082440SN/A 1092440SN/A // Machine operations 1102440SN/A 1112440SN/A void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 1122440SN/A int regnum); 1132440SN/A 1142440SN/A void restoreMachineReg(RegFile ®s, const AnyReg ®, 1152440SN/A int regnum); 1162440SN/A 1172440SN/A /** 1182440SN/A * Function to insure ISA semantics about 0 registers. 1192680Sktlim@umich.edu * @param tc The thread context. 1202440SN/A */ 1212680Sktlim@umich.edu template <class TC> 1222680Sktlim@umich.edu void zeroRegisters(TC *tc); 1232440SN/A 1243961Sgblack@eecs.umich.edu // Alpha IPR register accessors 1253961Sgblack@eecs.umich.edu inline bool PcPAL(Addr addr) { return addr & 0x3; } 1264194Ssaidi@eecs.umich.edu inline void startupCPU(ThreadContext *tc, int cpuId) { 1274194Ssaidi@eecs.umich.edu tc->activate(0); 1284194Ssaidi@eecs.umich.edu } 1292440SN/A#if FULL_SYSTEM 1302440SN/A 1312440SN/A //////////////////////////////////////////////////////////////////////// 1322440SN/A // 1332440SN/A // Translation stuff 1342440SN/A // 1352440SN/A 1362467SN/A inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 1372440SN/A 1382440SN/A // User Virtual 1392467SN/A inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 1402440SN/A 1412440SN/A // Kernel Direct Mapped 1422467SN/A inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 1432467SN/A inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 1442440SN/A 1452440SN/A // Kernel Virtual 1462467SN/A inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 1472440SN/A 1482467SN/A inline Addr 1492440SN/A TruncPage(Addr addr) 1502440SN/A { return addr & ~(PageBytes - 1); } 1512440SN/A 1522467SN/A inline Addr 1532440SN/A RoundPage(Addr addr) 1542440SN/A { return (addr + PageBytes - 1) & ~(PageBytes - 1); } 1552440SN/A 1562680Sktlim@umich.edu void initCPU(ThreadContext *tc, int cpuId); 1572680Sktlim@umich.edu void initIPRs(ThreadContext *tc, int cpuId); 1582440SN/A 1592440SN/A /** 1602440SN/A * Function to check for and process any interrupts. 1612680Sktlim@umich.edu * @param tc The thread context. 1622440SN/A */ 1632680Sktlim@umich.edu template <class TC> 1642680Sktlim@umich.edu void processInterrupts(TC *tc); 1652440SN/A#endif 1662440SN/A 1672440SN/A} // namespace AlphaISA 1682440SN/A 1692440SN/A#endif 170