utility.hh revision 2440
12686Sksewell@umich.edu/* 22686Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35268Sksewell@umich.edu * All rights reserved. 45268Sksewell@umich.edu * 55268Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65268Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75268Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95268Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115268Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125268Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135268Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145268Sksewell@umich.edu * this software without specific prior written permission. 155268Sksewell@umich.edu * 165268Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175268Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185268Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195268Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205268Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215268Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225268Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235268Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245268Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255268Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265268Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275268Sksewell@umich.edu */ 285268Sksewell@umich.edu 295268Sksewell@umich.edu#ifndef __ARCH_ALPHA_UTILITY_HH__ 302706Sksewell@umich.edu#define __ARCH_ALPHA_UTILITY_HH__ 312686Sksewell@umich.edu 322686Sksewell@umich.edu#include "config/full_system.hh" 332686Sksewell@umich.edu#include "arch/alpha/types.hh" 342686Sksewell@umich.edu#include "arch/alpha/constants.hh" 352686Sksewell@umich.edu#include "arch/alpha/registerfile.hh" 362686Sksewell@umich.edu#include "base/misc.hh" 372686Sksewell@umich.edu 382741Sksewell@umich.edunamespace AlphaISA 392686Sksewell@umich.edu{ 404661Sksewell@umich.edu 412686Sksewell@umich.edu static inline ExtMachInst 422686Sksewell@umich.edu makeExtMI(MachInst inst, const uint64_t &pc) { 432686Sksewell@umich.edu#if FULL_SYSTEM 442686Sksewell@umich.edu ExtMachInst ext_inst = inst; 454661Sksewell@umich.edu if (pc && 0x1) 464661Sksewell@umich.edu return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); 472686Sksewell@umich.edu else 482686Sksewell@umich.edu return ext_inst; 492686Sksewell@umich.edu#else 504661Sksewell@umich.edu return ExtMachInst(inst); 514661Sksewell@umich.edu#endif 524661Sksewell@umich.edu } 534661Sksewell@umich.edu 544661Sksewell@umich.edu static inline bool isCallerSaveIntegerRegister(unsigned int reg) { 554661Sksewell@umich.edu panic("register classification not implemented"); 564661Sksewell@umich.edu return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 574661Sksewell@umich.edu } 584661Sksewell@umich.edu 594661Sksewell@umich.edu static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 604661Sksewell@umich.edu panic("register classification not implemented"); 614661Sksewell@umich.edu return (reg >= 9 && reg <= 15); 624661Sksewell@umich.edu } 634661Sksewell@umich.edu 644661Sksewell@umich.edu static inline bool isCallerSaveFloatRegister(unsigned int reg) { 654661Sksewell@umich.edu panic("register classification not implemented"); 664661Sksewell@umich.edu return false; 672686Sksewell@umich.edu } 682686Sksewell@umich.edu 692686Sksewell@umich.edu static inline bool isCalleeSaveFloatRegister(unsigned int reg) { 702686Sksewell@umich.edu panic("register classification not implemented"); 714661Sksewell@umich.edu return false; 724661Sksewell@umich.edu } 734661Sksewell@umich.edu 744661Sksewell@umich.edu static inline Addr alignAddress(const Addr &addr, 755269Sksewell@umich.edu unsigned int nbytes) { 764661Sksewell@umich.edu return (addr & ~(nbytes - 1)); 775269Sksewell@umich.edu } 784661Sksewell@umich.edu 794661Sksewell@umich.edu // Instruction address compression hooks 804661Sksewell@umich.edu static inline Addr realPCToFetchPC(const Addr &addr) { 814661Sksewell@umich.edu return addr; 824661Sksewell@umich.edu } 834661Sksewell@umich.edu 844661Sksewell@umich.edu static inline Addr fetchPCToRealPC(const Addr &addr) { 854661Sksewell@umich.edu return addr; 864661Sksewell@umich.edu } 879554Sandreas.hansson@arm.com 889554Sandreas.hansson@arm.com // the size of "fetched" instructions (not necessarily the size 899554Sandreas.hansson@arm.com // of real instructions for PISA) 909554Sandreas.hansson@arm.com static inline size_t fetchInstSize() { 919554Sandreas.hansson@arm.com return sizeof(MachInst); 929554Sandreas.hansson@arm.com } 939554Sandreas.hansson@arm.com 949554Sandreas.hansson@arm.com static inline MachInst makeRegisterCopy(int dest, int src) { 959554Sandreas.hansson@arm.com panic("makeRegisterCopy not implemented"); 969554Sandreas.hansson@arm.com return 0; 979554Sandreas.hansson@arm.com } 984661Sksewell@umich.edu 9910196SCurtis.Dunham@arm.com // Machine operations 1006376Sgblack@eecs.umich.edu 1016376Sgblack@eecs.umich.edu void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 1026376Sgblack@eecs.umich.edu int regnum); 1034661Sksewell@umich.edu 1046383Sgblack@eecs.umich.edu void restoreMachineReg(RegFile ®s, const AnyReg ®, 10512104Snathanael.premillieu@arm.com int regnum); 10612104Snathanael.premillieu@arm.com 1076383Sgblack@eecs.umich.edu /** 1086383Sgblack@eecs.umich.edu * Function to insure ISA semantics about 0 registers. 1096383Sgblack@eecs.umich.edu * @param xc The execution context. 1104661Sksewell@umich.edu */ 1114661Sksewell@umich.edu template <class XC> 11210196SCurtis.Dunham@arm.com void zeroRegisters(XC *xc); 1134661Sksewell@umich.edu 1146383Sgblack@eecs.umich.edu#if FULL_SYSTEM 1154661Sksewell@umich.edu // Alpha IPR register accessors 1164661Sksewell@umich.edu static inline bool PcPAL(Addr addr) { return addr & 0x1; } 1174661Sksewell@umich.edu 1184661Sksewell@umich.edu //////////////////////////////////////////////////////////////////////// 11910196SCurtis.Dunham@arm.com // 1202686Sksewell@umich.edu // Translation stuff 1214661Sksewell@umich.edu // 1228607Sgblack@eecs.umich.edu 1234661Sksewell@umich.edu static inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 1244661Sksewell@umich.edu 1254661Sksewell@umich.edu // User Virtual 1266376Sgblack@eecs.umich.edu static inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 1276376Sgblack@eecs.umich.edu 1286376Sgblack@eecs.umich.edu // Kernel Direct Mapped 1296376Sgblack@eecs.umich.edu extern inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 1306376Sgblack@eecs.umich.edu static inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 1314661Sksewell@umich.edu 1326376Sgblack@eecs.umich.edu // Kernel Virtual 1336376Sgblack@eecs.umich.edu static inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 1344661Sksewell@umich.edu 1354661Sksewell@umich.edu static inline Addr 1366376Sgblack@eecs.umich.edu TruncPage(Addr addr) 1374661Sksewell@umich.edu { return addr & ~(PageBytes - 1); } 1386376Sgblack@eecs.umich.edu 1394661Sksewell@umich.edu static inline Addr 1404661Sksewell@umich.edu RoundPage(Addr addr) 1414661Sksewell@umich.edu { return (addr + PageBytes - 1) & ~(PageBytes - 1); } 1424661Sksewell@umich.edu 1434661Sksewell@umich.edu void initCPU(ExecContext *xc, int cpuId); 14410474Sandreas.hansson@arm.com void initIPRs(ExecContext *xc, int cpuId); 1454661Sksewell@umich.edu 1464661Sksewell@umich.edu /** 1474661Sksewell@umich.edu * Function to check for and process any interrupts. 1484661Sksewell@umich.edu * @param xc The execution context. 1494661Sksewell@umich.edu */ 1504661Sksewell@umich.edu template <class XC> 1514661Sksewell@umich.edu void processInterrupts(XC *xc); 1524661Sksewell@umich.edu#endif 1532686Sksewell@umich.edu 1542686Sksewell@umich.edu} // namespace AlphaISA 1552686Sksewell@umich.edu 1564661Sksewell@umich.edu#endif 15710196SCurtis.Dunham@arm.com