utility.cc revision 7693:f1db1000d957 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 *          Ali Saidi
30 */
31
32#include "arch/alpha/ev5.hh"
33#include "arch/alpha/utility.hh"
34
35#if FULL_SYSTEM
36#include "arch/alpha/vtophys.hh"
37#include "mem/vport.hh"
38#endif
39
40namespace AlphaISA {
41
42uint64_t
43getArgument(ThreadContext *tc, int &number, uint8_t size, bool fp)
44{
45#if FULL_SYSTEM
46    const int NumArgumentRegs = 6;
47    if (number < NumArgumentRegs) {
48        if (fp)
49            return tc->readFloatRegBits(16 + number);
50        else
51            return tc->readIntReg(16 + number);
52    } else {
53        Addr sp = tc->readIntReg(StackPointerReg);
54        VirtualPort *vp = tc->getVirtPort();
55        uint64_t arg = vp->read<uint64_t>(sp +
56                           (number-NumArgumentRegs) * sizeof(uint64_t));
57        return arg;
58    }
59#else
60    panic("getArgument() is Full system only\n");
61    M5_DUMMY_RETURN;
62#endif
63}
64
65void
66copyRegs(ThreadContext *src, ThreadContext *dest)
67{
68    // First loop through the integer registers.
69    for (int i = 0; i < NumIntRegs; ++i)
70        dest->setIntReg(i, src->readIntReg(i));
71
72    // Then loop through the floating point registers.
73    for (int i = 0; i < NumFloatRegs; ++i)
74        dest->setFloatRegBits(i, src->readFloatRegBits(i));
75
76    // Copy misc. registers
77    copyMiscRegs(src, dest);
78
79    // Lastly copy PC/NPC
80    dest->setPC(src->readPC());
81    dest->setNextPC(src->readNextPC());
82}
83
84void
85copyMiscRegs(ThreadContext *src, ThreadContext *dest)
86{
87    dest->setMiscRegNoEffect(MISCREG_FPCR,
88        src->readMiscRegNoEffect(MISCREG_FPCR));
89    dest->setMiscRegNoEffect(MISCREG_UNIQ,
90        src->readMiscRegNoEffect(MISCREG_UNIQ));
91    dest->setMiscRegNoEffect(MISCREG_LOCKFLAG,
92        src->readMiscRegNoEffect(MISCREG_LOCKFLAG));
93    dest->setMiscRegNoEffect(MISCREG_LOCKADDR,
94        src->readMiscRegNoEffect(MISCREG_LOCKADDR));
95
96    copyIprs(src, dest);
97}
98
99void
100skipFunction(ThreadContext *tc)
101{
102    Addr newpc = tc->readIntReg(ReturnAddressReg);
103    tc->setPC(newpc);
104    tc->setNextPC(tc->readPC() + sizeof(TheISA::MachInst));
105}
106
107
108} // namespace AlphaISA
109
110