utility.cc revision 6329
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Ali Saidi 30 */ 31 32#include "arch/alpha/utility.hh" 33 34#if FULL_SYSTEM 35#include "arch/alpha/vtophys.hh" 36#include "mem/vport.hh" 37#endif 38 39namespace AlphaISA { 40 41uint64_t 42getArgument(ThreadContext *tc, int number, bool fp) 43{ 44#if FULL_SYSTEM 45 const int NumArgumentRegs = 6; 46 if (number < NumArgumentRegs) { 47 if (fp) 48 return tc->readFloatRegBits(16 + number); 49 else 50 return tc->readIntReg(16 + number); 51 } else { 52 Addr sp = tc->readIntReg(StackPointerReg); 53 VirtualPort *vp = tc->getVirtPort(); 54 uint64_t arg = vp->read<uint64_t>(sp + 55 (number-NumArgumentRegs) * sizeof(uint64_t)); 56 return arg; 57 } 58#else 59 panic("getArgument() is Full system only\n"); 60 M5_DUMMY_RETURN; 61#endif 62} 63 64void 65copyRegs(ThreadContext *src, ThreadContext *dest) 66{ 67 // First loop through the integer registers. 68 for (int i = 0; i < NumIntRegs; ++i) 69 dest->setIntReg(i, src->readIntReg(i)); 70 71 // Then loop through the floating point registers. 72 for (int i = 0; i < NumFloatRegs; ++i) 73 dest->setFloatRegBits(i, src->readFloatRegBits(i)); 74 75 // Copy misc. registers 76 copyMiscRegs(src, dest); 77 78 // Lastly copy PC/NPC 79 dest->setPC(src->readPC()); 80 dest->setNextPC(src->readNextPC()); 81} 82 83void 84copyMiscRegs(ThreadContext *src, ThreadContext *dest) 85{ 86 dest->setMiscRegNoEffect(MISCREG_FPCR, 87 src->readMiscRegNoEffect(MISCREG_FPCR)); 88 dest->setMiscRegNoEffect(MISCREG_UNIQ, 89 src->readMiscRegNoEffect(MISCREG_UNIQ)); 90 dest->setMiscRegNoEffect(MISCREG_LOCKFLAG, 91 src->readMiscRegNoEffect(MISCREG_LOCKFLAG)); 92 dest->setMiscRegNoEffect(MISCREG_LOCKADDR, 93 src->readMiscRegNoEffect(MISCREG_LOCKADDR)); 94 95 copyIprs(src, dest); 96} 97 98} // namespace AlphaISA 99 100