tlb.cc revision 8229
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302SN/A * Andrew Schultz 312SN/A */ 321388SN/A 332SN/A#include <string> 342SN/A#include <vector> 352SN/A 361191SN/A#include "arch/alpha/faults.hh" 371191SN/A#include "arch/alpha/pagetable.hh" 381191SN/A#include "arch/alpha/tlb.hh" 391388SN/A#include "base/inifile.hh" 405529Snate@binkert.org#include "base/str.hh" 411717SN/A#include "base/trace.hh" 422651Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 432680Sktlim@umich.edu 441977SN/Ausing namespace std; 455529Snate@binkert.org 463144Shsul@eecs.umich.edunamespace AlphaISA { 472190SN/A 4856SN/A/////////////////////////////////////////////////////////////////////// 492190SN/A// 502SN/A// Alpha TLB 512359SN/A// 522359SN/A 532359SN/A#ifdef DEBUG 542SN/Abool uncacheBit39 = false; 552SN/Abool uncacheBit40 = false; 562SN/A#endif 572SN/A 582SN/A#define MODE2MASK(X) (1 << (X)) 592SN/A 602SN/ATLB::TLB(const Params *p) 612SN/A : BaseTLB(p), size(p->size), nlu(0) 622SN/A{ 635606Snate@binkert.org table = new TlbEntry[size]; 645606Snate@binkert.org memset(table, 0, sizeof(TlbEntry[size])); 655606Snate@binkert.org flushCache(); 663126Sktlim@umich.edu} 673126Sktlim@umich.edu 685606Snate@binkert.orgTLB::~TLB() 693126Sktlim@umich.edu{ 703126Sktlim@umich.edu if (table) 712356SN/A delete [] table; 722356SN/A} 732356SN/A 742367SN/Avoid 752356SN/ATLB::regStats() 765100Ssaidi@eecs.umich.edu{ 772367SN/A fetch_hits 782356SN/A .name(name() + ".fetch_hits") 792356SN/A .desc("ITB hits"); 802356SN/A fetch_misses 812367SN/A .name(name() + ".fetch_misses") 822367SN/A .desc("ITB misses"); 832367SN/A fetch_acv 842367SN/A .name(name() + ".fetch_acv") 852356SN/A .desc("ITB acv"); 865606Snate@binkert.org fetch_accesses 872356SN/A .name(name() + ".fetch_accesses") 882356SN/A .desc("ITB accesses"); 892356SN/A 905336Shines@cs.fsu.edu fetch_accesses = fetch_hits + fetch_misses; 912356SN/A 924873Sstever@eecs.umich.edu read_hits 932356SN/A .name(name() + ".read_hits") 942356SN/A .desc("DTB read hits") 951858SN/A ; 961400SN/A 975712Shsul@eecs.umich.edu read_misses 985712Shsul@eecs.umich.edu .name(name() + ".read_misses") 995529Snate@binkert.org .desc("DTB read misses") 1003661Srdreslin@umich.edu ; 1012SN/A 1021400SN/A read_acv 1035712Shsul@eecs.umich.edu .name(name() + ".read_acv") 1045529Snate@binkert.org .desc("DTB read access violations") 1053661Srdreslin@umich.edu ; 1062SN/A 1072SN/A read_accesses 1082359SN/A .name(name() + ".read_accesses") 1091062SN/A .desc("DTB read accesses") 1105712Shsul@eecs.umich.edu ; 1115712Shsul@eecs.umich.edu 1125712Shsul@eecs.umich.edu write_hits 1135712Shsul@eecs.umich.edu .name(name() + ".write_hits") 1145712Shsul@eecs.umich.edu .desc("DTB write hits") 1152SN/A ; 1162SN/A 1172SN/A write_misses 1185712Shsul@eecs.umich.edu .name(name() + ".write_misses") 1195712Shsul@eecs.umich.edu .desc("DTB write misses") 1202SN/A ; 1212SN/A 1222SN/A write_acv 1232SN/A .name(name() + ".write_acv") 1241354SN/A .desc("DTB write access violations") 1252SN/A ; 126503SN/A 1272SN/A write_accesses 1282SN/A .name(name() + ".write_accesses") 1292SN/A .desc("DTB write accesses") 1302SN/A ; 1315606Snate@binkert.org 1325606Snate@binkert.org data_hits 1335606Snate@binkert.org .name(name() + ".data_hits") 1345606Snate@binkert.org .desc("DTB hits") 1355606Snate@binkert.org ; 1365606Snate@binkert.org 1375606Snate@binkert.org data_misses 1382SN/A .name(name() + ".data_misses") 1391400SN/A .desc("DTB misses") 1405606Snate@binkert.org ; 1415606Snate@binkert.org 1422SN/A data_acv 1432SN/A .name(name() + ".data_acv") 1442SN/A .desc("DTB access violations") 1452SN/A ; 1462SN/A 1475606Snate@binkert.org data_accesses 1485606Snate@binkert.org .name(name() + ".data_accesses") 1495606Snate@binkert.org .desc("DTB accesses") 1505606Snate@binkert.org ; 1512SN/A 1522SN/A data_hits = read_hits + write_hits; 153124SN/A data_misses = read_misses + write_misses; 1541354SN/A data_acv = read_acv + write_acv; 155124SN/A data_accesses = read_accesses + write_accesses; 156124SN/A} 157124SN/A 158124SN/A// look up an entry in the TLB 159124SN/ATlbEntry * 160124SN/ATLB::lookup(Addr vpn, uint8_t asn) 1615606Snate@binkert.org{ 1625606Snate@binkert.org // assume not found... 1635606Snate@binkert.org TlbEntry *retval = NULL; 1645606Snate@binkert.org 1655606Snate@binkert.org if (EntryCache[0]) { 1665606Snate@binkert.org if (vpn == EntryCache[0]->tag && 1675606Snate@binkert.org (EntryCache[0]->asma || EntryCache[0]->asn == asn)) 168124SN/A retval = EntryCache[0]; 1691400SN/A else if (EntryCache[1]) { 1705606Snate@binkert.org if (vpn == EntryCache[1]->tag && 171124SN/A (EntryCache[1]->asma || EntryCache[1]->asn == asn)) 172124SN/A retval = EntryCache[1]; 173124SN/A else if (EntryCache[2] && vpn == EntryCache[2]->tag && 174124SN/A (EntryCache[2]->asma || EntryCache[2]->asn == asn)) 175124SN/A retval = EntryCache[2]; 1765606Snate@binkert.org } 1775606Snate@binkert.org } 1785606Snate@binkert.org 1795606Snate@binkert.org if (retval == NULL) { 180124SN/A PageTable::const_iterator i = lookupTable.find(vpn); 181124SN/A if (i != lookupTable.end()) { 1821191SN/A while (i->first == vpn) { 1835529Snate@binkert.org int index = i->second; 1841388SN/A TlbEntry *entry = &table[index]; 1851191SN/A assert(entry->valid); 1865529Snate@binkert.org if (vpn == entry->tag && (entry->asma || entry->asn == asn)) { 1871191SN/A retval = updateCache(entry); 1885529Snate@binkert.org break; 1891191SN/A } 1901191SN/A 1915606Snate@binkert.org ++i; 1925606Snate@binkert.org } 1935606Snate@binkert.org } 1941191SN/A } 1951191SN/A 1961917SN/A DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 1971917SN/A retval ? "hit" : "miss", retval ? retval->ppn : 0); 1985529Snate@binkert.org return retval; 1995529Snate@binkert.org} 2001917SN/A 2015529Snate@binkert.orgFault 2021917SN/ATLB::checkCacheability(RequestPtr &req, bool itb) 2031191SN/A{ 2041191SN/A // in Alpha, cacheability is controlled by upper-level bits of the 2051191SN/A // physical address 2061191SN/A 2071191SN/A /* 2081191SN/A * We support having the uncacheable bit in either bit 39 or bit 2091191SN/A * 40. The Turbolaser platform (and EV5) support having the bit 2101191SN/A * in 39, but Tsunami (which Linux assumes uses an EV6) generates 2111191SN/A * accesses with the bit in 40. So we must check for both, but we 2121191SN/A * have debug flags to catch a weird case where both are used, 2131191SN/A * which shouldn't happen. 2141129SN/A */ 2151129SN/A 2161129SN/A 2175529Snate@binkert.org if (req->getPaddr() & PAddrUncachedBit43) { 2182680Sktlim@umich.edu // IPR memory space not implemented 2191129SN/A if (PAddrIprSpace(req->getPaddr())) { 220180SN/A return new UnimpFault("IPR memory space not implemented!"); 2212SN/A } else { 2221917SN/A // mark request as uncacheable 2231917SN/A req->setFlags(Request::UNCACHEABLE); 2241917SN/A 2255529Snate@binkert.org // Clear bits 42:35 of the physical address (10-2 in 2265606Snate@binkert.org // Tsunami manual) 2271917SN/A req->setPaddr(req->getPaddr() & PAddrUncachedMask); 2282356SN/A } 2295529Snate@binkert.org // We shouldn't be able to read from an uncachable address in Alpha as 2305606Snate@binkert.org // we don't have a ROM and we don't want to try to fetch from a device 2315606Snate@binkert.org // register as we destroy any data that is clear-on-read. 2325606Snate@binkert.org if (req->isUncacheable() && itb) 2332356SN/A return new UnimpFault("CPU trying to fetch from uncached I/O"); 2341917SN/A 2351917SN/A } 2361917SN/A return NoFault; 2371917SN/A} 2382SN/A 2392SN/A 240729SN/A// insert a new TLB entry 241707SN/Avoid 242707SN/ATLB::insert(Addr addr, TlbEntry &entry) 243707SN/A{ 244707SN/A flushCache(); 245707SN/A VAddr vaddr = addr; 246707SN/A if (table[nlu].valid) { 2472680Sktlim@umich.edu Addr oldvpn = table[nlu].tag; 2482SN/A PageTable::iterator i = lookupTable.find(oldvpn); 2492SN/A 2502SN/A if (i == lookupTable.end()) 2512SN/A panic("TLB entry not found in lookupTable"); 2522680Sktlim@umich.edu 2532SN/A int index; 2542SN/A while ((index = i->second) != nlu) { 2552680Sktlim@umich.edu if (table[index].tag != oldvpn) 2562190SN/A panic("TLB entry not found in lookupTable"); 2572190SN/A 2582190SN/A ++i; 2592SN/A } 2602SN/A 2613495Sktlim@umich.edu DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 2623495Sktlim@umich.edu 2633495Sktlim@umich.edu lookupTable.erase(i); 2643661Srdreslin@umich.edu } 2653495Sktlim@umich.edu 2663661Srdreslin@umich.edu DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn); 2673495Sktlim@umich.edu 2683495Sktlim@umich.edu table[nlu] = entry; 2693495Sktlim@umich.edu table[nlu].tag = vaddr.vpn(); 2703495Sktlim@umich.edu table[nlu].valid = true; 2713495Sktlim@umich.edu 2723495Sktlim@umich.edu lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 2733495Sktlim@umich.edu nextnlu(); 2744599Sacolyte@umich.edu} 2754599Sacolyte@umich.edu 2763661Srdreslin@umich.eduvoid 2773495Sktlim@umich.eduTLB::flushAll() 2783495Sktlim@umich.edu{ 2793495Sktlim@umich.edu DPRINTF(TLB, "flushAll\n"); 2803495Sktlim@umich.edu memset(table, 0, sizeof(TlbEntry[size])); 281180SN/A flushCache(); 282180SN/A lookupTable.clear(); 2832680Sktlim@umich.edu nlu = 0; 284180SN/A} 2852680Sktlim@umich.edu 2862680Sktlim@umich.eduvoid 2872378SN/ATLB::flushProcesses() 2885714Shsul@eecs.umich.edu{ 2895713Shsul@eecs.umich.edu flushCache(); 2905714Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.begin(); 291180SN/A PageTable::iterator end = lookupTable.end(); 292180SN/A while (i != end) { 293180SN/A int index = i->second; 294180SN/A TlbEntry *entry = &table[index]; 295180SN/A assert(entry->valid); 2964000Ssaidi@eecs.umich.edu 2974000Ssaidi@eecs.umich.edu // we can't increment i after we erase it, so save a copy and 2984000Ssaidi@eecs.umich.edu // increment it to get the next entry now 2994000Ssaidi@eecs.umich.edu PageTable::iterator cur = i; 3004000Ssaidi@eecs.umich.edu ++i; 3014000Ssaidi@eecs.umich.edu 3024000Ssaidi@eecs.umich.edu if (!entry->asma) { 3034000Ssaidi@eecs.umich.edu DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, 3044000Ssaidi@eecs.umich.edu entry->tag, entry->ppn); 3054000Ssaidi@eecs.umich.edu entry->valid = false; 306180SN/A lookupTable.erase(cur); 3072798Sktlim@umich.edu } 308180SN/A } 3092359SN/A} 3102359SN/A 3112359SN/Avoid 3125606Snate@binkert.orgTLB::flushAddr(Addr addr, uint8_t asn) 3132359SN/A{ 314180SN/A flushCache(); 315180SN/A VAddr vaddr = addr; 316180SN/A 3174192Sktlim@umich.edu PageTable::iterator i = lookupTable.find(vaddr.vpn()); 318180SN/A if (i == lookupTable.end()) 3192680Sktlim@umich.edu return; 320180SN/A 3215712Shsul@eecs.umich.edu while (i != lookupTable.end() && i->first == vaddr.vpn()) { 3225712Shsul@eecs.umich.edu int index = i->second; 3232680Sktlim@umich.edu TlbEntry *entry = &table[index]; 3242680Sktlim@umich.edu assert(entry->valid); 3252680Sktlim@umich.edu 326180SN/A if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) { 3272680Sktlim@umich.edu DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 3282651Ssaidi@eecs.umich.edu entry->ppn); 3292680Sktlim@umich.edu 3302651Ssaidi@eecs.umich.edu // invalidate this entry 3315714Shsul@eecs.umich.edu entry->valid = false; 3325715Shsul@eecs.umich.edu 3335714Shsul@eecs.umich.edu lookupTable.erase(i++); 3342359SN/A } else { 3355217Ssaidi@eecs.umich.edu ++i; 3365217Ssaidi@eecs.umich.edu } 337180SN/A } 338605SN/A} 3391858SN/A 3403520Sgblack@eecs.umich.edu 3412254SN/Avoid 3422680Sktlim@umich.eduTLB::serialize(ostream &os) 3432680Sktlim@umich.edu{ 3442254SN/A SERIALIZE_SCALAR(size); 3454947Snate@binkert.org SERIALIZE_SCALAR(nlu); 3465606Snate@binkert.org 347612SN/A for (int i = 0; i < size; i++) { 3484192Sktlim@umich.edu nameOut(os, csprintf("%s.Entry%d", name(), i)); 3494192Sktlim@umich.edu table[i].serialize(os); 3504192Sktlim@umich.edu } 3514192Sktlim@umich.edu} 3525476Snate@binkert.org 3535476Snate@binkert.orgvoid 3544192Sktlim@umich.eduTLB::unserialize(Checkpoint *cp, const string §ion) 3555476Snate@binkert.org{ 3564192Sktlim@umich.edu UNSERIALIZE_SCALAR(size); 3574192Sktlim@umich.edu UNSERIALIZE_SCALAR(nlu); 3585476Snate@binkert.org 3595476Snate@binkert.org for (int i = 0; i < size; i++) { 3604192Sktlim@umich.edu table[i].unserialize(cp, csprintf("%s.Entry%d", section, i)); 3615476Snate@binkert.org if (table[i].valid) { 3624192Sktlim@umich.edu lookupTable.insert(make_pair(table[i].tag, i)); 363180SN/A } 364180SN/A } 365180SN/A} 3661858SN/A 3675536Srstrong@hp.comFault 3685606Snate@binkert.orgTLB::translateInst(RequestPtr req, ThreadContext *tc) 3691917SN/A{ 3701917SN/A //If this is a pal pc, then set PHYSICAL 3711917SN/A if (FULL_SYSTEM && PcPAL(req->getPC())) 3721917SN/A req->setFlags(Request::PHYSICAL); 3731917SN/A 3742680Sktlim@umich.edu if (PcPAL(req->getPC())) { 3752680Sktlim@umich.edu // strip off PAL PC marker (lsb is 1) 3762680Sktlim@umich.edu req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 3771917SN/A fetch_hits++; 3782254SN/A return NoFault; 3795606Snate@binkert.org } 3801917SN/A 3811917SN/A if (req->getFlags() & Request::PHYSICAL) { 3822SN/A req->setPaddr(req->getVaddr()); 3835704Snate@binkert.org } else { 3842SN/A // verify that this is a good virtual address 3855647Sgblack@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 3862SN/A fetch_acv++; 3872SN/A return new ItbAcvFault(req->getVaddr()); 3882SN/A } 3895704Snate@binkert.org 3902SN/A 3915647Sgblack@eecs.umich.edu // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 3922SN/A // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 3932SN/A if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { 3942SN/A // only valid in kernel mode 3955704Snate@binkert.org if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 3962SN/A mode_kernel) { 3975704Snate@binkert.org fetch_acv++; 3982SN/A return new ItbAcvFault(req->getVaddr()); 3992SN/A } 400921SN/A 401921SN/A req->setPaddr(req->getVaddr() & PAddrImplMask); 402921SN/A 4034000Ssaidi@eecs.umich.edu // sign extend the physical address properly 4045647Sgblack@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 405921SN/A req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 406921SN/A else 407921SN/A req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 408921SN/A } else { 409921SN/A // not a physical address: need to look up pte 4104000Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 4115647Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), 412921SN/A asn); 413921SN/A 4142SN/A if (!entry) { 4152SN/A fetch_misses++; 4161191SN/A return new ItbPageFault(req->getVaddr()); 4171191SN/A } 4181191SN/A 4191191SN/A req->setPaddr((entry->ppn << PageShift) + 4201191SN/A (VAddr(req->getVaddr()).offset() 4211191SN/A & ~3)); 4221191SN/A 4231191SN/A // check permissions for this access 4241191SN/A if (!(entry->xre & 4251191SN/A (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { 4261191SN/A // instruction access fault 4271191SN/A fetch_acv++; 4281191SN/A return new ItbAcvFault(req->getVaddr()); 4291191SN/A } 4301191SN/A 4311191SN/A fetch_hits++; 4321191SN/A } 4331191SN/A } 4341191SN/A 4351191SN/A // check that the physical address is ok (catch bad physical addresses) 4361191SN/A if (req->getPaddr() & ~PAddrImplMask) 4371191SN/A return genMachineCheckFault(); 4381191SN/A 4391191SN/A return checkCacheability(req, true); 4401191SN/A 4411191SN/A} 442 443Fault 444TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 445{ 446 mode_type mode = 447 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 448 449 /** 450 * Check for alignment faults 451 */ 452 if (req->getVaddr() & (req->getSize() - 1)) { 453 DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(), 454 req->getSize()); 455 uint64_t flags = write ? MM_STAT_WR_MASK : 0; 456 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); 457 } 458 459 if (PcPAL(tc->pcState().pc())) { 460 mode = (req->getFlags() & Request::ALTMODE) ? 461 (mode_type)ALT_MODE_AM( 462 tc->readMiscRegNoEffect(IPR_ALT_MODE)) 463 : mode_kernel; 464 } 465 466 if (req->getFlags() & Request::PHYSICAL) { 467 req->setPaddr(req->getVaddr()); 468 } else { 469 // verify that this is a good virtual address 470 if (!validVirtualAddress(req->getVaddr())) { 471 if (write) { write_acv++; } else { read_acv++; } 472 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 473 MM_STAT_BAD_VA_MASK | 474 MM_STAT_ACV_MASK; 475 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 476 } 477 478 // Check for "superpage" mapping 479 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { 480 // only valid in kernel mode 481 if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 482 mode_kernel) { 483 if (write) { write_acv++; } else { read_acv++; } 484 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 485 MM_STAT_ACV_MASK); 486 487 return new DtbAcvFault(req->getVaddr(), req->getFlags(), 488 flags); 489 } 490 491 req->setPaddr(req->getVaddr() & PAddrImplMask); 492 493 // sign extend the physical address properly 494 if (req->getPaddr() & PAddrUncachedBit40) 495 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 496 else 497 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 498 } else { 499 if (write) 500 write_accesses++; 501 else 502 read_accesses++; 503 504 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 505 506 // not a physical address: need to look up pte 507 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn); 508 509 if (!entry) { 510 // page fault 511 if (write) { write_misses++; } else { read_misses++; } 512 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 513 MM_STAT_DTB_MISS_MASK; 514 return (req->getFlags() & Request::VPTE) ? 515 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), 516 flags)) : 517 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), 518 flags)); 519 } 520 521 req->setPaddr((entry->ppn << PageShift) + 522 VAddr(req->getVaddr()).offset()); 523 524 if (write) { 525 if (!(entry->xwe & MODE2MASK(mode))) { 526 // declare the instruction access fault 527 write_acv++; 528 uint64_t flags = MM_STAT_WR_MASK | 529 MM_STAT_ACV_MASK | 530 (entry->fonw ? MM_STAT_FONW_MASK : 0); 531 return new DtbPageFault(req->getVaddr(), req->getFlags(), 532 flags); 533 } 534 if (entry->fonw) { 535 write_acv++; 536 uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK; 537 return new DtbPageFault(req->getVaddr(), req->getFlags(), 538 flags); 539 } 540 } else { 541 if (!(entry->xre & MODE2MASK(mode))) { 542 read_acv++; 543 uint64_t flags = MM_STAT_ACV_MASK | 544 (entry->fonr ? MM_STAT_FONR_MASK : 0); 545 return new DtbAcvFault(req->getVaddr(), req->getFlags(), 546 flags); 547 } 548 if (entry->fonr) { 549 read_acv++; 550 uint64_t flags = MM_STAT_FONR_MASK; 551 return new DtbPageFault(req->getVaddr(), req->getFlags(), 552 flags); 553 } 554 } 555 } 556 557 if (write) 558 write_hits++; 559 else 560 read_hits++; 561 } 562 563 // check that the physical address is ok (catch bad physical addresses) 564 if (req->getPaddr() & ~PAddrImplMask) 565 return genMachineCheckFault(); 566 567 return checkCacheability(req); 568} 569 570TlbEntry & 571TLB::index(bool advance) 572{ 573 TlbEntry *entry = &table[nlu]; 574 575 if (advance) 576 nextnlu(); 577 578 return *entry; 579} 580 581Fault 582TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 583{ 584 if (mode == Execute) 585 return translateInst(req, tc); 586 else 587 return translateData(req, tc, mode == Write); 588} 589 590void 591TLB::translateTiming(RequestPtr req, ThreadContext *tc, 592 Translation *translation, Mode mode) 593{ 594 assert(translation); 595 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 596} 597 598} // namespace AlphaISA 599 600AlphaISA::TLB * 601AlphaTLBParams::create() 602{ 603 return new AlphaISA::TLB(this); 604} 605