tlb.cc revision 4957:f858d0b8ef99
112SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 312SN/A * All rights reserved. 412SN/A * 512SN/A * Redistribution and use in source and binary forms, with or without 612SN/A * modification, are permitted provided that the following conditions are 712SN/A * met: redistributions of source code must retain the above copyright 812SN/A * notice, this list of conditions and the following disclaimer; 912SN/A * redistributions in binary form must reproduce the above copyright 1012SN/A * notice, this list of conditions and the following disclaimer in the 1112SN/A * documentation and/or other materials provided with the distribution; 1212SN/A * neither the name of the copyright holders nor the names of its 1312SN/A * contributors may be used to endorse or promote products derived from 1412SN/A * this software without specific prior written permission. 1512SN/A * 1612SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 3012SN/A * Andrew Schultz 3112SN/A */ 3212SN/A 3312SN/A#include <string> 34468SN/A#include <vector> 35468SN/A 36468SN/A#include "arch/alpha/pagetable.hh" 37661SN/A#include "arch/alpha/tlb.hh" 38468SN/A#include "arch/alpha/faults.hh" 392634Sstever@eecs.umich.edu#include "base/inifile.hh" 40468SN/A#include "base/str.hh" 4156SN/A#include "base/trace.hh" 422439SN/A#include "config/alpha_tlaser.hh" 4312SN/A#include "cpu/thread_context.hh" 4456SN/A#include "params/AlphaDTB.hh" 4512SN/A#include "params/AlphaITB.hh" 4656SN/A 4712SN/Ausing namespace std; 482423SN/Ausing namespace EV5; 492423SN/A 5012SN/Anamespace AlphaISA { 5112SN/A/////////////////////////////////////////////////////////////////////// 5212SN/A// 5312SN/A// Alpha TLB 5412SN/A// 5512SN/A#ifdef DEBUG 56443SN/Abool uncacheBit39 = false; 57443SN/Abool uncacheBit40 = false; 582207SN/A#endif 592207SN/A 60443SN/A#define MODE2MASK(X) (1 << (X)) 61468SN/A 621708SN/ATLB::TLB(const string &name, int s) 631708SN/A : SimObject(name), size(s), nlu(0) 64443SN/A{ 65468SN/A table = new PTE[size]; 66443SN/A memset(table, 0, sizeof(PTE[size])); 67468SN/A flushCache(); 68443SN/A} 69443SN/A 70468SN/ATLB::~TLB() 71468SN/A{ 72443SN/A if (table) 73443SN/A delete [] table; 74443SN/A} 752476SN/A 762207SN/A// look up an entry in the TLB 772207SN/APTE * 782207SN/ATLB::lookup(Addr vpn, uint8_t asn) const 792207SN/A{ 802207SN/A // assume not found... 812207SN/A PTE *retval = NULL; 822620SN/A 832207SN/A if (PTECache[0] && vpn == PTECache[0]->tag && 842207SN/A (PTECache[0]->asma || PTECache[0]->asn == asn)) 852207SN/A retval = PTECache[0]; 862472SN/A else if (PTECache[1] && vpn == PTECache[1]->tag && 872207SN/A (PTECache[1]->asma || PTECache[1]->asn == asn)) 882207SN/A retval = PTECache[1]; 892207SN/A else if (PTECache[2] && vpn == PTECache[2]->tag && 902600SN/A (PTECache[2]->asma || PTECache[2]->asn == asn)) 912207SN/A retval = PTECache[2]; 922207SN/A else { 932207SN/A PageTable::const_iterator i = lookupTable.find(vpn); 942207SN/A if (i != lookupTable.end()) { 952207SN/A while (i->first == vpn) { 962207SN/A int index = i->second; 972238SN/A PTE *pte = &table[index]; 982207SN/A assert(pte->valid); 992207SN/A if (vpn == pte->tag && (pte->asma || pte->asn == asn)) { 1002207SN/A retval = pte; 1012207SN/A break; 1022207SN/A } 1032238SN/A 1042207SN/A ++i; 1052207SN/A } 1062238SN/A } 1072207SN/A } 1082207SN/A 1092207SN/A DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 1102207SN/A retval ? "hit" : "miss", retval ? retval->ppn : 0); 1112238SN/A return retval; 1122238SN/A} 1132600SN/A 1142238SN/A 1152238SN/AFault 1162238SN/ATLB::checkCacheability(RequestPtr &req) 1172238SN/A{ 1182238SN/A// in Alpha, cacheability is controlled by upper-level bits of the 1192238SN/A// physical address 1202238SN/A 1212238SN/A/* 1222238SN/A * We support having the uncacheable bit in either bit 39 or bit 40. 1232238SN/A * The Turbolaser platform (and EV5) support having the bit in 39, but 1242600SN/A * Tsunami (which Linux assumes uses an EV6) generates accesses with 1252238SN/A * the bit in 40. So we must check for both, but we have debug flags 1262238SN/A * to catch a weird case where both are used, which shouldn't happen. 1272238SN/A */ 1282238SN/A 1292238SN/A 1302238SN/A#if ALPHA_TLASER 1312238SN/A if (req->getPaddr() & PAddrUncachedBit39) 1322238SN/A#else 1332238SN/A if (req->getPaddr() & PAddrUncachedBit43) 1342238SN/A#endif 1352238SN/A { 1362238SN/A // IPR memory space not implemented 1372238SN/A if (PAddrIprSpace(req->getPaddr())) { 1382238SN/A return new UnimpFault("IPR memory space not implemented!"); 1392238SN/A } else { 1402238SN/A // mark request as uncacheable 1412238SN/A req->setFlags(req->getFlags() | UNCACHEABLE); 1422238SN/A 1432238SN/A#if !ALPHA_TLASER 1442238SN/A // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) 1452238SN/A req->setPaddr(req->getPaddr() & PAddrUncachedMask); 1462238SN/A#endif 1472600SN/A } 1482600SN/A } 1492600SN/A return NoFault; 1502600SN/A} 1512600SN/A 1522238SN/A 1532238SN/A// insert a new TLB entry 1542238SN/Avoid 1552472SN/ATLB::insert(Addr addr, PTE &pte) 1562238SN/A{ 1572207SN/A flushCache(); 15812SN/A VAddr vaddr = addr; 15912SN/A if (table[nlu].valid) { 16012SN/A Addr oldvpn = table[nlu].tag; 16112SN/A PageTable::iterator i = lookupTable.find(oldvpn); 16212SN/A 163360SN/A if (i == lookupTable.end()) 164360SN/A panic("TLB entry not found in lookupTable"); 165360SN/A 166443SN/A int index; 16712SN/A while ((index = i->second) != nlu) { 168443SN/A if (table[index].tag != oldvpn) 169443SN/A panic("TLB entry not found in lookupTable"); 17012SN/A 171468SN/A ++i; 1721708SN/A } 1731708SN/A 17412SN/A DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 175468SN/A 176443SN/A lookupTable.erase(i); 177468SN/A } 178443SN/A 17912SN/A DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn); 180468SN/A 181468SN/A table[nlu] = pte; 182443SN/A table[nlu].tag = vaddr.vpn(); 18312SN/A table[nlu].valid = true; 18412SN/A 185468SN/A lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 18612SN/A nextnlu(); 1872472SN/A} 188468SN/A 189468SN/Avoid 190468SN/ATLB::flushAll() 191468SN/A{ 192468SN/A DPRINTF(TLB, "flushAll\n"); 193468SN/A memset(table, 0, sizeof(PTE[size])); 194468SN/A flushCache(); 195468SN/A lookupTable.clear(); 196468SN/A nlu = 0; 197468SN/A} 198468SN/A 199468SN/Avoid 200468SN/ATLB::flushProcesses() 201468SN/A{ 202468SN/A flushCache(); 203468SN/A PageTable::iterator i = lookupTable.begin(); 204468SN/A PageTable::iterator end = lookupTable.end(); 205468SN/A while (i != end) { 2062420SN/A int index = i->second; 207468SN/A PTE *pte = &table[index]; 208468SN/A assert(pte->valid); 209468SN/A 210468SN/A // we can't increment i after we erase it, so save a copy and 211468SN/A // increment it to get the next entry now 212468SN/A PageTable::iterator cur = i; 2132420SN/A ++i; 2142476SN/A 215468SN/A if (!pte->asma) { 216468SN/A DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn); 2172420SN/A pte->valid = false; 218468SN/A lookupTable.erase(cur); 219468SN/A } 220468SN/A } 221468SN/A} 222468SN/A 223468SN/Avoid 224468SN/ATLB::flushAddr(Addr addr, uint8_t asn) 225468SN/A{ 2262420SN/A flushCache(); 2272476SN/A VAddr vaddr = addr; 2282476SN/A 2292476SN/A PageTable::iterator i = lookupTable.find(vaddr.vpn()); 2302476SN/A if (i == lookupTable.end()) 231468SN/A return; 232468SN/A 233468SN/A while (i != lookupTable.end() && i->first == vaddr.vpn()) { 234468SN/A int index = i->second; 235468SN/A PTE *pte = &table[index]; 236468SN/A assert(pte->valid); 237468SN/A 238468SN/A if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) { 239468SN/A DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 240468SN/A pte->ppn); 241443SN/A 242443SN/A // invalidate this entry 243468SN/A pte->valid = false; 24412SN/A 24512SN/A lookupTable.erase(i++); 24612SN/A } else { 24712SN/A ++i; 248468SN/A } 24912SN/A } 250443SN/A} 251766SN/A 252443SN/A 253443SN/Avoid 254443SN/ATLB::serialize(ostream &os) 255443SN/A{ 256443SN/A SERIALIZE_SCALAR(size); 257443SN/A SERIALIZE_SCALAR(nlu); 258443SN/A 259443SN/A for (int i = 0; i < size; i++) { 260443SN/A nameOut(os, csprintf("%s.PTE%d", name(), i)); 261443SN/A table[i].serialize(os); 262468SN/A } 2631708SN/A} 2641708SN/A 265443SN/Avoid 266468SN/ATLB::unserialize(Checkpoint *cp, const string §ion) 267443SN/A{ 268443SN/A UNSERIALIZE_SCALAR(size); 269443SN/A UNSERIALIZE_SCALAR(nlu); 270443SN/A 271468SN/A for (int i = 0; i < size; i++) { 272454SN/A table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 273443SN/A if (table[i].valid) { 274468SN/A lookupTable.insert(make_pair(table[i].tag, i)); 275468SN/A } 276443SN/A } 277443SN/A} 278468SN/A 279443SN/A 280443SN/A/////////////////////////////////////////////////////////////////////// 281443SN/A// 282443SN/A// Alpha ITB 283443SN/A// 284468SN/AITB::ITB(const std::string &name, int size) 285468SN/A : TLB(name, size) 286443SN/A{} 287836SN/A 288468SN/A 289468SN/Avoid 290443SN/AITB::regStats() 291443SN/A{ 292443SN/A hits 293454SN/A .name(name() + ".hits") 294454SN/A .desc("ITB hits"); 295443SN/A misses 296443SN/A .name(name() + ".misses") 297443SN/A .desc("ITB misses"); 298443SN/A acv 299443SN/A .name(name() + ".acv") 30012SN/A .desc("ITB acv"); 30112SN/A accesses 30212SN/A .name(name() + ".accesses") 303468SN/A .desc("ITB accesses"); 304468SN/A 305468SN/A accesses = hits + misses; 306468SN/A} 307468SN/A 308468SN/A 30912SN/AFault 31012SN/AITB::translate(RequestPtr &req, ThreadContext *tc) const 311468SN/A{ 31212SN/A //If this is a pal pc, then set PHYSICAL 313 if(FULL_SYSTEM && PcPAL(req->getPC())) 314 req->setFlags(req->getFlags() | PHYSICAL); 315 316 if (PcPAL(req->getPC())) { 317 // strip off PAL PC marker (lsb is 1) 318 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 319 hits++; 320 return NoFault; 321 } 322 323 if (req->getFlags() & PHYSICAL) { 324 req->setPaddr(req->getVaddr()); 325 } else { 326 // verify that this is a good virtual address 327 if (!validVirtualAddress(req->getVaddr())) { 328 acv++; 329 return new ItbAcvFault(req->getVaddr()); 330 } 331 332 333 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 334 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 335#if ALPHA_TLASER 336 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 337 VAddrSpaceEV5(req->getVaddr()) == 2) 338#else 339 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 340#endif 341 { 342 // only valid in kernel mode 343 if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 344 mode_kernel) { 345 acv++; 346 return new ItbAcvFault(req->getVaddr()); 347 } 348 349 req->setPaddr(req->getVaddr() & PAddrImplMask); 350 351#if !ALPHA_TLASER 352 // sign extend the physical address properly 353 if (req->getPaddr() & PAddrUncachedBit40) 354 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 355 else 356 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 357#endif 358 359 } else { 360 // not a physical address: need to look up pte 361 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 362 PTE *pte = lookup(VAddr(req->getVaddr()).vpn(), 363 asn); 364 365 if (!pte) { 366 misses++; 367 return new ItbPageFault(req->getVaddr()); 368 } 369 370 req->setPaddr((pte->ppn << PageShift) + 371 (VAddr(req->getVaddr()).offset() 372 & ~3)); 373 374 // check permissions for this access 375 if (!(pte->xre & 376 (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { 377 // instruction access fault 378 acv++; 379 return new ItbAcvFault(req->getVaddr()); 380 } 381 382 hits++; 383 } 384 } 385 386 // check that the physical address is ok (catch bad physical addresses) 387 if (req->getPaddr() & ~PAddrImplMask) 388 return genMachineCheckFault(); 389 390 return checkCacheability(req); 391 392} 393 394/////////////////////////////////////////////////////////////////////// 395// 396// Alpha DTB 397// 398 DTB::DTB(const std::string &name, int size) 399 : TLB(name, size) 400{} 401 402void 403DTB::regStats() 404{ 405 read_hits 406 .name(name() + ".read_hits") 407 .desc("DTB read hits") 408 ; 409 410 read_misses 411 .name(name() + ".read_misses") 412 .desc("DTB read misses") 413 ; 414 415 read_acv 416 .name(name() + ".read_acv") 417 .desc("DTB read access violations") 418 ; 419 420 read_accesses 421 .name(name() + ".read_accesses") 422 .desc("DTB read accesses") 423 ; 424 425 write_hits 426 .name(name() + ".write_hits") 427 .desc("DTB write hits") 428 ; 429 430 write_misses 431 .name(name() + ".write_misses") 432 .desc("DTB write misses") 433 ; 434 435 write_acv 436 .name(name() + ".write_acv") 437 .desc("DTB write access violations") 438 ; 439 440 write_accesses 441 .name(name() + ".write_accesses") 442 .desc("DTB write accesses") 443 ; 444 445 hits 446 .name(name() + ".hits") 447 .desc("DTB hits") 448 ; 449 450 misses 451 .name(name() + ".misses") 452 .desc("DTB misses") 453 ; 454 455 acv 456 .name(name() + ".acv") 457 .desc("DTB access violations") 458 ; 459 460 accesses 461 .name(name() + ".accesses") 462 .desc("DTB accesses") 463 ; 464 465 hits = read_hits + write_hits; 466 misses = read_misses + write_misses; 467 acv = read_acv + write_acv; 468 accesses = read_accesses + write_accesses; 469} 470 471Fault 472DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const 473{ 474 Addr pc = tc->readPC(); 475 476 mode_type mode = 477 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 478 479 480 /** 481 * Check for alignment faults 482 */ 483 if (req->getVaddr() & (req->getSize() - 1)) { 484 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 485 req->getSize()); 486 uint64_t flags = write ? MM_STAT_WR_MASK : 0; 487 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); 488 } 489 490 if (PcPAL(pc)) { 491 mode = (req->getFlags() & ALTMODE) ? 492 (mode_type)ALT_MODE_AM( 493 tc->readMiscRegNoEffect(IPR_ALT_MODE)) 494 : mode_kernel; 495 } 496 497 if (req->getFlags() & PHYSICAL) { 498 req->setPaddr(req->getVaddr()); 499 } else { 500 // verify that this is a good virtual address 501 if (!validVirtualAddress(req->getVaddr())) { 502 if (write) { write_acv++; } else { read_acv++; } 503 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 504 MM_STAT_BAD_VA_MASK | 505 MM_STAT_ACV_MASK; 506 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 507 } 508 509 // Check for "superpage" mapping 510#if ALPHA_TLASER 511 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 512 VAddrSpaceEV5(req->getVaddr()) == 2) 513#else 514 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 515#endif 516 { 517 518 // only valid in kernel mode 519 if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 520 mode_kernel) { 521 if (write) { write_acv++; } else { read_acv++; } 522 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 523 MM_STAT_ACV_MASK); 524 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 525 } 526 527 req->setPaddr(req->getVaddr() & PAddrImplMask); 528 529#if !ALPHA_TLASER 530 // sign extend the physical address properly 531 if (req->getPaddr() & PAddrUncachedBit40) 532 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 533 else 534 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 535#endif 536 537 } else { 538 if (write) 539 write_accesses++; 540 else 541 read_accesses++; 542 543 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 544 545 // not a physical address: need to look up pte 546 PTE *pte = lookup(VAddr(req->getVaddr()).vpn(), 547 asn); 548 549 if (!pte) { 550 // page fault 551 if (write) { write_misses++; } else { read_misses++; } 552 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 553 MM_STAT_DTB_MISS_MASK; 554 return (req->getFlags() & VPTE) ? 555 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), 556 flags)) : 557 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), 558 flags)); 559 } 560 561 req->setPaddr((pte->ppn << PageShift) + 562 VAddr(req->getVaddr()).offset()); 563 564 if (write) { 565 if (!(pte->xwe & MODE2MASK(mode))) { 566 // declare the instruction access fault 567 write_acv++; 568 uint64_t flags = MM_STAT_WR_MASK | 569 MM_STAT_ACV_MASK | 570 (pte->fonw ? MM_STAT_FONW_MASK : 0); 571 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 572 } 573 if (pte->fonw) { 574 write_acv++; 575 uint64_t flags = MM_STAT_WR_MASK | 576 MM_STAT_FONW_MASK; 577 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 578 } 579 } else { 580 if (!(pte->xre & MODE2MASK(mode))) { 581 read_acv++; 582 uint64_t flags = MM_STAT_ACV_MASK | 583 (pte->fonr ? MM_STAT_FONR_MASK : 0); 584 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 585 } 586 if (pte->fonr) { 587 read_acv++; 588 uint64_t flags = MM_STAT_FONR_MASK; 589 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 590 } 591 } 592 } 593 594 if (write) 595 write_hits++; 596 else 597 read_hits++; 598 } 599 600 // check that the physical address is ok (catch bad physical addresses) 601 if (req->getPaddr() & ~PAddrImplMask) 602 return genMachineCheckFault(); 603 604 return checkCacheability(req); 605} 606 607PTE & 608TLB::index(bool advance) 609{ 610 PTE *pte = &table[nlu]; 611 612 if (advance) 613 nextnlu(); 614 615 return *pte; 616} 617 618/* end namespace AlphaISA */ } 619 620AlphaISA::ITB * 621AlphaITBParams::create() 622{ 623 return new AlphaISA::ITB(name, size); 624} 625 626AlphaISA::DTB * 627AlphaDTBParams::create() 628{ 629 return new AlphaISA::DTB(name, size); 630} 631