tlb.cc revision 4428:05bab139ebe0
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 * Andrew Schultz 31 */ 32 33#include <string> 34#include <vector> 35 36#include "arch/alpha/pagetable.hh" 37#include "arch/alpha/tlb.hh" 38#include "arch/alpha/faults.hh" 39#include "base/inifile.hh" 40#include "base/str.hh" 41#include "base/trace.hh" 42#include "config/alpha_tlaser.hh" 43#include "cpu/thread_context.hh" 44#include "sim/builder.hh" 45 46using namespace std; 47using namespace EV5; 48 49namespace AlphaISA { 50/////////////////////////////////////////////////////////////////////// 51// 52// Alpha TLB 53// 54#ifdef DEBUG 55bool uncacheBit39 = false; 56bool uncacheBit40 = false; 57#endif 58 59#define MODE2MASK(X) (1 << (X)) 60 61TLB::TLB(const string &name, int s) 62 : SimObject(name), size(s), nlu(0) 63{ 64 table = new PTE[size]; 65 memset(table, 0, sizeof(PTE[size])); 66} 67 68TLB::~TLB() 69{ 70 if (table) 71 delete [] table; 72} 73 74// look up an entry in the TLB 75PTE * 76TLB::lookup(Addr vpn, uint8_t asn) const 77{ 78 // assume not found... 79 PTE *retval = NULL; 80 81 PageTable::const_iterator i = lookupTable.find(vpn); 82 if (i != lookupTable.end()) { 83 while (i->first == vpn) { 84 int index = i->second; 85 PTE *pte = &table[index]; 86 assert(pte->valid); 87 if (vpn == pte->tag && (pte->asma || pte->asn == asn)) { 88 retval = pte; 89 break; 90 } 91 92 ++i; 93 } 94 } 95 96 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 97 retval ? "hit" : "miss", retval ? retval->ppn : 0); 98 return retval; 99} 100 101 102Fault 103TLB::checkCacheability(RequestPtr &req) 104{ 105// in Alpha, cacheability is controlled by upper-level bits of the 106// physical address 107 108/* 109 * We support having the uncacheable bit in either bit 39 or bit 40. 110 * The Turbolaser platform (and EV5) support having the bit in 39, but 111 * Tsunami (which Linux assumes uses an EV6) generates accesses with 112 * the bit in 40. So we must check for both, but we have debug flags 113 * to catch a weird case where both are used, which shouldn't happen. 114 */ 115 116 117#if ALPHA_TLASER 118 if (req->getPaddr() & PAddrUncachedBit39) 119#else 120 if (req->getPaddr() & PAddrUncachedBit43) 121#endif 122 { 123 // IPR memory space not implemented 124 if (PAddrIprSpace(req->getPaddr())) { 125 return new UnimpFault("IPR memory space not implemented!"); 126 } else { 127 // mark request as uncacheable 128 req->setFlags(req->getFlags() | UNCACHEABLE); 129 130#if !ALPHA_TLASER 131 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) 132 req->setPaddr(req->getPaddr() & PAddrUncachedMask); 133#endif 134 } 135 } 136 return NoFault; 137} 138 139 140// insert a new TLB entry 141void 142TLB::insert(Addr addr, PTE &pte) 143{ 144 VAddr vaddr = addr; 145 if (table[nlu].valid) { 146 Addr oldvpn = table[nlu].tag; 147 PageTable::iterator i = lookupTable.find(oldvpn); 148 149 if (i == lookupTable.end()) 150 panic("TLB entry not found in lookupTable"); 151 152 int index; 153 while ((index = i->second) != nlu) { 154 if (table[index].tag != oldvpn) 155 panic("TLB entry not found in lookupTable"); 156 157 ++i; 158 } 159 160 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 161 162 lookupTable.erase(i); 163 } 164 165 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn); 166 167 table[nlu] = pte; 168 table[nlu].tag = vaddr.vpn(); 169 table[nlu].valid = true; 170 171 lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 172 nextnlu(); 173} 174 175void 176TLB::flushAll() 177{ 178 DPRINTF(TLB, "flushAll\n"); 179 memset(table, 0, sizeof(PTE[size])); 180 lookupTable.clear(); 181 nlu = 0; 182} 183 184void 185TLB::flushProcesses() 186{ 187 PageTable::iterator i = lookupTable.begin(); 188 PageTable::iterator end = lookupTable.end(); 189 while (i != end) { 190 int index = i->second; 191 PTE *pte = &table[index]; 192 assert(pte->valid); 193 194 // we can't increment i after we erase it, so save a copy and 195 // increment it to get the next entry now 196 PageTable::iterator cur = i; 197 ++i; 198 199 if (!pte->asma) { 200 DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn); 201 pte->valid = false; 202 lookupTable.erase(cur); 203 } 204 } 205} 206 207void 208TLB::flushAddr(Addr addr, uint8_t asn) 209{ 210 VAddr vaddr = addr; 211 212 PageTable::iterator i = lookupTable.find(vaddr.vpn()); 213 if (i == lookupTable.end()) 214 return; 215 216 while (i != lookupTable.end() && i->first == vaddr.vpn()) { 217 int index = i->second; 218 PTE *pte = &table[index]; 219 assert(pte->valid); 220 221 if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) { 222 DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 223 pte->ppn); 224 225 // invalidate this entry 226 pte->valid = false; 227 228 lookupTable.erase(i++); 229 } else { 230 ++i; 231 } 232 } 233} 234 235 236void 237TLB::serialize(ostream &os) 238{ 239 SERIALIZE_SCALAR(size); 240 SERIALIZE_SCALAR(nlu); 241 242 for (int i = 0; i < size; i++) { 243 nameOut(os, csprintf("%s.PTE%d", name(), i)); 244 table[i].serialize(os); 245 } 246} 247 248void 249TLB::unserialize(Checkpoint *cp, const string §ion) 250{ 251 UNSERIALIZE_SCALAR(size); 252 UNSERIALIZE_SCALAR(nlu); 253 254 for (int i = 0; i < size; i++) { 255 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 256 if (table[i].valid) { 257 lookupTable.insert(make_pair(table[i].tag, i)); 258 } 259 } 260} 261 262 263/////////////////////////////////////////////////////////////////////// 264// 265// Alpha ITB 266// 267ITB::ITB(const std::string &name, int size) 268 : TLB(name, size) 269{} 270 271 272void 273ITB::regStats() 274{ 275 hits 276 .name(name() + ".hits") 277 .desc("ITB hits"); 278 misses 279 .name(name() + ".misses") 280 .desc("ITB misses"); 281 acv 282 .name(name() + ".acv") 283 .desc("ITB acv"); 284 accesses 285 .name(name() + ".accesses") 286 .desc("ITB accesses"); 287 288 accesses = hits + misses; 289} 290 291 292Fault 293ITB::translate(RequestPtr &req, ThreadContext *tc) const 294{ 295 if (PcPAL(req->getPC())) { 296 // strip off PAL PC marker (lsb is 1) 297 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 298 hits++; 299 return NoFault; 300 } 301 302 if (req->getFlags() & PHYSICAL) { 303 req->setPaddr(req->getVaddr()); 304 } else { 305 // verify that this is a good virtual address 306 if (!validVirtualAddress(req->getVaddr())) { 307 acv++; 308 return new ItbAcvFault(req->getVaddr()); 309 } 310 311 312 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 313 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 314#if ALPHA_TLASER 315 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 316 VAddrSpaceEV5(req->getVaddr()) == 2) 317#else 318 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 319#endif 320 { 321 // only valid in kernel mode 322 if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 323 mode_kernel) { 324 acv++; 325 return new ItbAcvFault(req->getVaddr()); 326 } 327 328 req->setPaddr(req->getVaddr() & PAddrImplMask); 329 330#if !ALPHA_TLASER 331 // sign extend the physical address properly 332 if (req->getPaddr() & PAddrUncachedBit40) 333 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 334 else 335 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 336#endif 337 338 } else { 339 // not a physical address: need to look up pte 340 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 341 PTE *pte = lookup(VAddr(req->getVaddr()).vpn(), 342 asn); 343 344 if (!pte) { 345 misses++; 346 return new ItbPageFault(req->getVaddr()); 347 } 348 349 req->setPaddr((pte->ppn << PageShift) + 350 (VAddr(req->getVaddr()).offset() 351 & ~3)); 352 353 // check permissions for this access 354 if (!(pte->xre & 355 (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { 356 // instruction access fault 357 acv++; 358 return new ItbAcvFault(req->getVaddr()); 359 } 360 361 hits++; 362 } 363 } 364 365 // check that the physical address is ok (catch bad physical addresses) 366 if (req->getPaddr() & ~PAddrImplMask) 367 return genMachineCheckFault(); 368 369 return checkCacheability(req); 370 371} 372 373/////////////////////////////////////////////////////////////////////// 374// 375// Alpha DTB 376// 377 DTB::DTB(const std::string &name, int size) 378 : TLB(name, size) 379{} 380 381void 382DTB::regStats() 383{ 384 read_hits 385 .name(name() + ".read_hits") 386 .desc("DTB read hits") 387 ; 388 389 read_misses 390 .name(name() + ".read_misses") 391 .desc("DTB read misses") 392 ; 393 394 read_acv 395 .name(name() + ".read_acv") 396 .desc("DTB read access violations") 397 ; 398 399 read_accesses 400 .name(name() + ".read_accesses") 401 .desc("DTB read accesses") 402 ; 403 404 write_hits 405 .name(name() + ".write_hits") 406 .desc("DTB write hits") 407 ; 408 409 write_misses 410 .name(name() + ".write_misses") 411 .desc("DTB write misses") 412 ; 413 414 write_acv 415 .name(name() + ".write_acv") 416 .desc("DTB write access violations") 417 ; 418 419 write_accesses 420 .name(name() + ".write_accesses") 421 .desc("DTB write accesses") 422 ; 423 424 hits 425 .name(name() + ".hits") 426 .desc("DTB hits") 427 ; 428 429 misses 430 .name(name() + ".misses") 431 .desc("DTB misses") 432 ; 433 434 acv 435 .name(name() + ".acv") 436 .desc("DTB access violations") 437 ; 438 439 accesses 440 .name(name() + ".accesses") 441 .desc("DTB accesses") 442 ; 443 444 hits = read_hits + write_hits; 445 misses = read_misses + write_misses; 446 acv = read_acv + write_acv; 447 accesses = read_accesses + write_accesses; 448} 449 450Fault 451DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const 452{ 453 Addr pc = tc->readPC(); 454 455 mode_type mode = 456 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 457 458 459 /** 460 * Check for alignment faults 461 */ 462 if (req->getVaddr() & (req->getSize() - 1)) { 463 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 464 req->getSize()); 465 uint64_t flags = write ? MM_STAT_WR_MASK : 0; 466 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); 467 } 468 469 if (PcPAL(pc)) { 470 mode = (req->getFlags() & ALTMODE) ? 471 (mode_type)ALT_MODE_AM( 472 tc->readMiscRegNoEffect(IPR_ALT_MODE)) 473 : mode_kernel; 474 } 475 476 if (req->getFlags() & PHYSICAL) { 477 req->setPaddr(req->getVaddr()); 478 } else { 479 // verify that this is a good virtual address 480 if (!validVirtualAddress(req->getVaddr())) { 481 if (write) { write_acv++; } else { read_acv++; } 482 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 483 MM_STAT_BAD_VA_MASK | 484 MM_STAT_ACV_MASK; 485 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 486 } 487 488 // Check for "superpage" mapping 489#if ALPHA_TLASER 490 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 491 VAddrSpaceEV5(req->getVaddr()) == 2) 492#else 493 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 494#endif 495 { 496 497 // only valid in kernel mode 498 if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 499 mode_kernel) { 500 if (write) { write_acv++; } else { read_acv++; } 501 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 502 MM_STAT_ACV_MASK); 503 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 504 } 505 506 req->setPaddr(req->getVaddr() & PAddrImplMask); 507 508#if !ALPHA_TLASER 509 // sign extend the physical address properly 510 if (req->getPaddr() & PAddrUncachedBit40) 511 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 512 else 513 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 514#endif 515 516 } else { 517 if (write) 518 write_accesses++; 519 else 520 read_accesses++; 521 522 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 523 524 // not a physical address: need to look up pte 525 PTE *pte = lookup(VAddr(req->getVaddr()).vpn(), 526 asn); 527 528 if (!pte) { 529 // page fault 530 if (write) { write_misses++; } else { read_misses++; } 531 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 532 MM_STAT_DTB_MISS_MASK; 533 return (req->getFlags() & VPTE) ? 534 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), 535 flags)) : 536 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), 537 flags)); 538 } 539 540 req->setPaddr((pte->ppn << PageShift) + 541 VAddr(req->getVaddr()).offset()); 542 543 if (write) { 544 if (!(pte->xwe & MODE2MASK(mode))) { 545 // declare the instruction access fault 546 write_acv++; 547 uint64_t flags = MM_STAT_WR_MASK | 548 MM_STAT_ACV_MASK | 549 (pte->fonw ? MM_STAT_FONW_MASK : 0); 550 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 551 } 552 if (pte->fonw) { 553 write_acv++; 554 uint64_t flags = MM_STAT_WR_MASK | 555 MM_STAT_FONW_MASK; 556 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 557 } 558 } else { 559 if (!(pte->xre & MODE2MASK(mode))) { 560 read_acv++; 561 uint64_t flags = MM_STAT_ACV_MASK | 562 (pte->fonr ? MM_STAT_FONR_MASK : 0); 563 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 564 } 565 if (pte->fonr) { 566 read_acv++; 567 uint64_t flags = MM_STAT_FONR_MASK; 568 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 569 } 570 } 571 } 572 573 if (write) 574 write_hits++; 575 else 576 read_hits++; 577 } 578 579 // check that the physical address is ok (catch bad physical addresses) 580 if (req->getPaddr() & ~PAddrImplMask) 581 return genMachineCheckFault(); 582 583 return checkCacheability(req); 584} 585 586PTE & 587TLB::index(bool advance) 588{ 589 PTE *pte = &table[nlu]; 590 591 if (advance) 592 nextnlu(); 593 594 return *pte; 595} 596 597/* end namespace AlphaISA */ } 598 599DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB) 600 601BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 602 603 Param<int> size; 604 605END_DECLARE_SIM_OBJECT_PARAMS(ITB) 606 607BEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 608 609 INIT_PARAM_DFLT(size, "TLB size", 48) 610 611END_INIT_SIM_OBJECT_PARAMS(ITB) 612 613 614CREATE_SIM_OBJECT(ITB) 615{ 616 return new ITB(getInstanceName(), size); 617} 618 619REGISTER_SIM_OBJECT("AlphaITB", ITB) 620 621BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 622 623 Param<int> size; 624 625END_DECLARE_SIM_OBJECT_PARAMS(DTB) 626 627BEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 628 629 INIT_PARAM_DFLT(size, "TLB size", 64) 630 631END_INIT_SIM_OBJECT_PARAMS(DTB) 632 633 634CREATE_SIM_OBJECT(DTB) 635{ 636 return new DTB(getInstanceName(), size); 637} 638 639REGISTER_SIM_OBJECT("AlphaDTB", DTB) 640