tlb.cc revision 2984
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 * Andrew Schultz 31 */ 32 33#include <string> 34#include <vector> 35 36#include "arch/alpha/pagetable.hh" 37#include "arch/alpha/tlb.hh" 38#include "arch/alpha/faults.hh" 39#include "base/inifile.hh" 40#include "base/str.hh" 41#include "base/trace.hh" 42#include "config/alpha_tlaser.hh" 43#include "cpu/thread_context.hh" 44#include "sim/builder.hh" 45 46using namespace std; 47using namespace EV5; 48 49/////////////////////////////////////////////////////////////////////// 50// 51// Alpha TLB 52// 53#ifdef DEBUG 54bool uncacheBit39 = false; 55bool uncacheBit40 = false; 56#endif 57 58#define MODE2MASK(X) (1 << (X)) 59 60AlphaTLB::AlphaTLB(const string &name, int s) 61 : SimObject(name), size(s), nlu(0) 62{ 63 table = new AlphaISA::PTE[size]; 64 memset(table, 0, sizeof(AlphaISA::PTE[size])); 65} 66 67AlphaTLB::~AlphaTLB() 68{ 69 if (table) 70 delete [] table; 71} 72 73// look up an entry in the TLB 74AlphaISA::PTE * 75AlphaTLB::lookup(Addr vpn, uint8_t asn) const 76{ 77 // assume not found... 78 AlphaISA::PTE *retval = NULL; 79 80 PageTable::const_iterator i = lookupTable.find(vpn); 81 if (i != lookupTable.end()) { 82 while (i->first == vpn) { 83 int index = i->second; 84 AlphaISA::PTE *pte = &table[index]; 85 assert(pte->valid); 86 if (vpn == pte->tag && (pte->asma || pte->asn == asn)) { 87 retval = pte; 88 break; 89 } 90 91 ++i; 92 } 93 } 94 95 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 96 retval ? "hit" : "miss", retval ? retval->ppn : 0); 97 return retval; 98} 99 100 101Fault 102AlphaTLB::checkCacheability(RequestPtr &req) 103{ 104 // in Alpha, cacheability is controlled by upper-level bits of the 105 // physical address 106 107 /* 108 * We support having the uncacheable bit in either bit 39 or bit 40. 109 * The Turbolaser platform (and EV5) support having the bit in 39, but 110 * Tsunami (which Linux assumes uses an EV6) generates accesses with 111 * the bit in 40. So we must check for both, but we have debug flags 112 * to catch a weird case where both are used, which shouldn't happen. 113 */ 114 115 116#if ALPHA_TLASER 117 if (req->getPaddr() & PAddrUncachedBit39) { 118#else 119 if (req->getPaddr() & PAddrUncachedBit43) { 120#endif 121 // IPR memory space not implemented 122 if (PAddrIprSpace(req->getPaddr())) { 123 return new UnimpFault("IPR memory space not implemented!"); 124 } else { 125 // mark request as uncacheable 126 req->setFlags(req->getFlags() | UNCACHEABLE); 127 128#if !ALPHA_TLASER 129 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) 130 req->setPaddr(req->getPaddr() & PAddrUncachedMask); 131#endif 132 } 133 } 134 return NoFault; 135} 136 137 138// insert a new TLB entry 139void 140AlphaTLB::insert(Addr addr, AlphaISA::PTE &pte) 141{ 142 AlphaISA::VAddr vaddr = addr; 143 if (table[nlu].valid) { 144 Addr oldvpn = table[nlu].tag; 145 PageTable::iterator i = lookupTable.find(oldvpn); 146 147 if (i == lookupTable.end()) 148 panic("TLB entry not found in lookupTable"); 149 150 int index; 151 while ((index = i->second) != nlu) { 152 if (table[index].tag != oldvpn) 153 panic("TLB entry not found in lookupTable"); 154 155 ++i; 156 } 157 158 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 159 160 lookupTable.erase(i); 161 } 162 163 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn); 164 165 table[nlu] = pte; 166 table[nlu].tag = vaddr.vpn(); 167 table[nlu].valid = true; 168 169 lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 170 nextnlu(); 171} 172 173void 174AlphaTLB::flushAll() 175{ 176 DPRINTF(TLB, "flushAll\n"); 177 memset(table, 0, sizeof(AlphaISA::PTE[size])); 178 lookupTable.clear(); 179 nlu = 0; 180} 181 182void 183AlphaTLB::flushProcesses() 184{ 185 PageTable::iterator i = lookupTable.begin(); 186 PageTable::iterator end = lookupTable.end(); 187 while (i != end) { 188 int index = i->second; 189 AlphaISA::PTE *pte = &table[index]; 190 assert(pte->valid); 191 192 // we can't increment i after we erase it, so save a copy and 193 // increment it to get the next entry now 194 PageTable::iterator cur = i; 195 ++i; 196 197 if (!pte->asma) { 198 DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn); 199 pte->valid = false; 200 lookupTable.erase(cur); 201 } 202 } 203} 204 205void 206AlphaTLB::flushAddr(Addr addr, uint8_t asn) 207{ 208 AlphaISA::VAddr vaddr = addr; 209 210 PageTable::iterator i = lookupTable.find(vaddr.vpn()); 211 if (i == lookupTable.end()) 212 return; 213 214 while (i->first == vaddr.vpn()) { 215 int index = i->second; 216 AlphaISA::PTE *pte = &table[index]; 217 assert(pte->valid); 218 219 if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) { 220 DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 221 pte->ppn); 222 223 // invalidate this entry 224 pte->valid = false; 225 226 lookupTable.erase(i); 227 } 228 229 ++i; 230 } 231} 232 233 234void 235AlphaTLB::serialize(ostream &os) 236{ 237 SERIALIZE_SCALAR(size); 238 SERIALIZE_SCALAR(nlu); 239 240 for (int i = 0; i < size; i++) { 241 nameOut(os, csprintf("%s.PTE%d", name(), i)); 242 table[i].serialize(os); 243 } 244} 245 246void 247AlphaTLB::unserialize(Checkpoint *cp, const string §ion) 248{ 249 UNSERIALIZE_SCALAR(size); 250 UNSERIALIZE_SCALAR(nlu); 251 252 for (int i = 0; i < size; i++) { 253 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 254 if (table[i].valid) { 255 lookupTable.insert(make_pair(table[i].tag, i)); 256 } 257 } 258} 259 260 261/////////////////////////////////////////////////////////////////////// 262// 263// Alpha ITB 264// 265AlphaITB::AlphaITB(const std::string &name, int size) 266 : AlphaTLB(name, size) 267{} 268 269 270void 271AlphaITB::regStats() 272{ 273 hits 274 .name(name() + ".hits") 275 .desc("ITB hits"); 276 misses 277 .name(name() + ".misses") 278 .desc("ITB misses"); 279 acv 280 .name(name() + ".acv") 281 .desc("ITB acv"); 282 accesses 283 .name(name() + ".accesses") 284 .desc("ITB accesses"); 285 286 accesses = hits + misses; 287} 288 289 290Fault 291AlphaITB::translate(RequestPtr &req, ThreadContext *tc) const 292{ 293 if (AlphaISA::PcPAL(req->getVaddr())) { 294 // strip off PAL PC marker (lsb is 1) 295 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 296 hits++; 297 return NoFault; 298 } 299 300 if (req->getFlags() & PHYSICAL) { 301 req->setPaddr(req->getVaddr()); 302 } else { 303 // verify that this is a good virtual address 304 if (!validVirtualAddress(req->getVaddr())) { 305 acv++; 306 return new ItbAcvFault(req->getVaddr()); 307 } 308 309 310 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 311 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 312#if ALPHA_TLASER 313 if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && 314 VAddrSpaceEV5(req->getVaddr()) == 2) { 315#else 316 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { 317#endif 318 // only valid in kernel mode 319 if (ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM)) != 320 AlphaISA::mode_kernel) { 321 acv++; 322 return new ItbAcvFault(req->getVaddr()); 323 } 324 325 req->setPaddr(req->getVaddr() & PAddrImplMask); 326 327#if !ALPHA_TLASER 328 // sign extend the physical address properly 329 if (req->getPaddr() & PAddrUncachedBit40) 330 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 331 else 332 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 333#endif 334 335 } else { 336 // not a physical address: need to look up pte 337 int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN)); 338 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(), 339 asn); 340 341 if (!pte) { 342 misses++; 343 return new ItbPageFault(req->getVaddr()); 344 } 345 346 req->setPaddr((pte->ppn << AlphaISA::PageShift) + 347 (AlphaISA::VAddr(req->getVaddr()).offset() 348 & ~3)); 349 350 // check permissions for this access 351 if (!(pte->xre & 352 (1 << ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM))))) { 353 // instruction access fault 354 acv++; 355 return new ItbAcvFault(req->getVaddr()); 356 } 357 358 hits++; 359 } 360 } 361 362 // check that the physical address is ok (catch bad physical addresses) 363 if (req->getPaddr() & ~PAddrImplMask) 364 return genMachineCheckFault(); 365 366 return checkCacheability(req); 367 368} 369 370/////////////////////////////////////////////////////////////////////// 371// 372// Alpha DTB 373// 374AlphaDTB::AlphaDTB(const std::string &name, int size) 375 : AlphaTLB(name, size) 376{} 377 378void 379AlphaDTB::regStats() 380{ 381 read_hits 382 .name(name() + ".read_hits") 383 .desc("DTB read hits") 384 ; 385 386 read_misses 387 .name(name() + ".read_misses") 388 .desc("DTB read misses") 389 ; 390 391 read_acv 392 .name(name() + ".read_acv") 393 .desc("DTB read access violations") 394 ; 395 396 read_accesses 397 .name(name() + ".read_accesses") 398 .desc("DTB read accesses") 399 ; 400 401 write_hits 402 .name(name() + ".write_hits") 403 .desc("DTB write hits") 404 ; 405 406 write_misses 407 .name(name() + ".write_misses") 408 .desc("DTB write misses") 409 ; 410 411 write_acv 412 .name(name() + ".write_acv") 413 .desc("DTB write access violations") 414 ; 415 416 write_accesses 417 .name(name() + ".write_accesses") 418 .desc("DTB write accesses") 419 ; 420 421 hits 422 .name(name() + ".hits") 423 .desc("DTB hits") 424 ; 425 426 misses 427 .name(name() + ".misses") 428 .desc("DTB misses") 429 ; 430 431 acv 432 .name(name() + ".acv") 433 .desc("DTB access violations") 434 ; 435 436 accesses 437 .name(name() + ".accesses") 438 .desc("DTB accesses") 439 ; 440 441 hits = read_hits + write_hits; 442 misses = read_misses + write_misses; 443 acv = read_acv + write_acv; 444 accesses = read_accesses + write_accesses; 445} 446 447Fault 448AlphaDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const 449{ 450 Addr pc = tc->readPC(); 451 452 AlphaISA::mode_type mode = 453 (AlphaISA::mode_type)DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)); 454 455 456 /** 457 * Check for alignment faults 458 */ 459 if (req->getVaddr() & (req->getSize() - 1)) { 460 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 461 req->getSize()); 462 uint64_t flags = write ? MM_STAT_WR_MASK : 0; 463 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); 464 } 465 466 if (pc & 0x1) { 467 mode = (req->getFlags() & ALTMODE) ? 468 (AlphaISA::mode_type)ALT_MODE_AM( 469 tc->readMiscReg(AlphaISA::IPR_ALT_MODE)) 470 : AlphaISA::mode_kernel; 471 } 472 473 if (req->getFlags() & PHYSICAL) { 474 req->setPaddr(req->getVaddr()); 475 } else { 476 // verify that this is a good virtual address 477 if (!validVirtualAddress(req->getVaddr())) { 478 if (write) { write_acv++; } else { read_acv++; } 479 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 480 MM_STAT_BAD_VA_MASK | 481 MM_STAT_ACV_MASK; 482 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 483 } 484 485 // Check for "superpage" mapping 486#if ALPHA_TLASER 487 if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && 488 VAddrSpaceEV5(req->getVaddr()) == 2) { 489#else 490 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { 491#endif 492 493 // only valid in kernel mode 494 if (DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)) != 495 AlphaISA::mode_kernel) { 496 if (write) { write_acv++; } else { read_acv++; } 497 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 498 MM_STAT_ACV_MASK); 499 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 500 } 501 502 req->setPaddr(req->getVaddr() & PAddrImplMask); 503 504#if !ALPHA_TLASER 505 // sign extend the physical address properly 506 if (req->getPaddr() & PAddrUncachedBit40) 507 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 508 else 509 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 510#endif 511 512 } else { 513 if (write) 514 write_accesses++; 515 else 516 read_accesses++; 517 518 int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN)); 519 520 // not a physical address: need to look up pte 521 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(), 522 asn); 523 524 if (!pte) { 525 // page fault 526 if (write) { write_misses++; } else { read_misses++; } 527 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 528 MM_STAT_DTB_MISS_MASK; 529 return (req->getFlags() & VPTE) ? 530 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), 531 flags)) : 532 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), 533 flags)); 534 } 535 536 req->setPaddr((pte->ppn << AlphaISA::PageShift) + 537 AlphaISA::VAddr(req->getVaddr()).offset()); 538 539 if (write) { 540 if (!(pte->xwe & MODE2MASK(mode))) { 541 // declare the instruction access fault 542 write_acv++; 543 uint64_t flags = MM_STAT_WR_MASK | 544 MM_STAT_ACV_MASK | 545 (pte->fonw ? MM_STAT_FONW_MASK : 0); 546 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 547 } 548 if (pte->fonw) { 549 write_acv++; 550 uint64_t flags = MM_STAT_WR_MASK | 551 MM_STAT_FONW_MASK; 552 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 553 } 554 } else { 555 if (!(pte->xre & MODE2MASK(mode))) { 556 read_acv++; 557 uint64_t flags = MM_STAT_ACV_MASK | 558 (pte->fonr ? MM_STAT_FONR_MASK : 0); 559 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 560 } 561 if (pte->fonr) { 562 read_acv++; 563 uint64_t flags = MM_STAT_FONR_MASK; 564 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 565 } 566 } 567 } 568 569 if (write) 570 write_hits++; 571 else 572 read_hits++; 573 } 574 575 // check that the physical address is ok (catch bad physical addresses) 576 if (req->getPaddr() & ~PAddrImplMask) 577 return genMachineCheckFault(); 578 579 return checkCacheability(req); 580} 581 582AlphaISA::PTE & 583AlphaTLB::index(bool advance) 584{ 585 AlphaISA::PTE *pte = &table[nlu]; 586 587 if (advance) 588 nextnlu(); 589 590 return *pte; 591} 592 593DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB) 594 595BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) 596 597 Param<int> size; 598 599END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) 600 601BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB) 602 603 INIT_PARAM_DFLT(size, "TLB size", 48) 604 605END_INIT_SIM_OBJECT_PARAMS(AlphaITB) 606 607 608CREATE_SIM_OBJECT(AlphaITB) 609{ 610 return new AlphaITB(getInstanceName(), size); 611} 612 613REGISTER_SIM_OBJECT("AlphaITB", AlphaITB) 614 615BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) 616 617 Param<int> size; 618 619END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) 620 621BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB) 622 623 INIT_PARAM_DFLT(size, "TLB size", 64) 624 625END_INIT_SIM_OBJECT_PARAMS(AlphaDTB) 626 627 628CREATE_SIM_OBJECT(AlphaDTB) 629{ 630 return new AlphaDTB(getInstanceName(), size); 631} 632 633REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB) 634 635