tlb.cc revision 5140
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Andrew Schultz 312SN/A */ 322SN/A 332SN/A#include <string> 342SN/A#include <vector> 352SN/A 362984Sgblack@eecs.umich.edu#include "arch/alpha/pagetable.hh" 372171SN/A#include "arch/alpha/tlb.hh" 382984Sgblack@eecs.umich.edu#include "arch/alpha/faults.hh" 39146SN/A#include "base/inifile.hh" 40146SN/A#include "base/str.hh" 41146SN/A#include "base/trace.hh" 421858SN/A#include "config/alpha_tlaser.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 442SN/A 452SN/Ausing namespace std; 461147SN/Ausing namespace EV5; 472SN/A 484088Sbinkertn@umich.edunamespace AlphaISA { 493838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 503838Shsul@eecs.umich.edu// 513838Shsul@eecs.umich.edu// Alpha TLB 523838Shsul@eecs.umich.edu// 53860SN/A#ifdef DEBUG 543838Shsul@eecs.umich.edubool uncacheBit39 = false; 553838Shsul@eecs.umich.edubool uncacheBit40 = false; 56860SN/A#endif 57860SN/A 581147SN/A#define MODE2MASK(X) (1 << (X)) 591147SN/A 605034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 615034Smilesck@eecs.umich.edu : SimObject(p), size(p->size), nlu(0) 623838Shsul@eecs.umich.edu{ 635004Sgblack@eecs.umich.edu table = new TlbEntry[size]; 645004Sgblack@eecs.umich.edu memset(table, 0, sizeof(TlbEntry[size])); 654957Sacolyte@umich.edu flushCache(); 663838Shsul@eecs.umich.edu} 672SN/A 683838Shsul@eecs.umich.eduTLB::~TLB() 693838Shsul@eecs.umich.edu{ 703838Shsul@eecs.umich.edu if (table) 713838Shsul@eecs.umich.edu delete [] table; 723838Shsul@eecs.umich.edu} 732SN/A 743838Shsul@eecs.umich.edu// look up an entry in the TLB 755004Sgblack@eecs.umich.eduTlbEntry * 764967Sacolyte@umich.eduTLB::lookup(Addr vpn, uint8_t asn) 773838Shsul@eecs.umich.edu{ 783838Shsul@eecs.umich.edu // assume not found... 795004Sgblack@eecs.umich.edu TlbEntry *retval = NULL; 802SN/A 815004Sgblack@eecs.umich.edu if (EntryCache[0]) { 825004Sgblack@eecs.umich.edu if (vpn == EntryCache[0]->tag && 835004Sgblack@eecs.umich.edu (EntryCache[0]->asma || EntryCache[0]->asn == asn)) 845004Sgblack@eecs.umich.edu retval = EntryCache[0]; 855004Sgblack@eecs.umich.edu else if (EntryCache[1]) { 865004Sgblack@eecs.umich.edu if (vpn == EntryCache[1]->tag && 875004Sgblack@eecs.umich.edu (EntryCache[1]->asma || EntryCache[1]->asn == asn)) 885004Sgblack@eecs.umich.edu retval = EntryCache[1]; 895004Sgblack@eecs.umich.edu else if (EntryCache[2] && vpn == EntryCache[2]->tag && 905004Sgblack@eecs.umich.edu (EntryCache[2]->asma || EntryCache[2]->asn == asn)) 915004Sgblack@eecs.umich.edu retval = EntryCache[2]; 924962Sacolyte@umich.edu } 934962Sacolyte@umich.edu } 944962Sacolyte@umich.edu 954967Sacolyte@umich.edu if (retval == NULL) { 964957Sacolyte@umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 974957Sacolyte@umich.edu if (i != lookupTable.end()) { 984957Sacolyte@umich.edu while (i->first == vpn) { 994957Sacolyte@umich.edu int index = i->second; 1005004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 1015004Sgblack@eecs.umich.edu assert(entry->valid); 1025004Sgblack@eecs.umich.edu if (vpn == entry->tag && (entry->asma || entry->asn == asn)) { 1035004Sgblack@eecs.umich.edu retval = updateCache(entry); 1044957Sacolyte@umich.edu break; 1054957Sacolyte@umich.edu } 1064957Sacolyte@umich.edu 1074957Sacolyte@umich.edu ++i; 1081413SN/A } 1091413SN/A } 1102SN/A } 1112SN/A 1123838Shsul@eecs.umich.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 1133838Shsul@eecs.umich.edu retval ? "hit" : "miss", retval ? retval->ppn : 0); 1143838Shsul@eecs.umich.edu return retval; 1153838Shsul@eecs.umich.edu} 1162SN/A 1172SN/A 1183838Shsul@eecs.umich.eduFault 1193838Shsul@eecs.umich.eduTLB::checkCacheability(RequestPtr &req) 1203838Shsul@eecs.umich.edu{ 1213838Shsul@eecs.umich.edu// in Alpha, cacheability is controlled by upper-level bits of the 1223838Shsul@eecs.umich.edu// physical address 1233838Shsul@eecs.umich.edu 1243838Shsul@eecs.umich.edu/* 1253838Shsul@eecs.umich.edu * We support having the uncacheable bit in either bit 39 or bit 40. 1263838Shsul@eecs.umich.edu * The Turbolaser platform (and EV5) support having the bit in 39, but 1273838Shsul@eecs.umich.edu * Tsunami (which Linux assumes uses an EV6) generates accesses with 1283838Shsul@eecs.umich.edu * the bit in 40. So we must check for both, but we have debug flags 1293838Shsul@eecs.umich.edu * to catch a weird case where both are used, which shouldn't happen. 1303838Shsul@eecs.umich.edu */ 1313838Shsul@eecs.umich.edu 1323838Shsul@eecs.umich.edu 1333838Shsul@eecs.umich.edu#if ALPHA_TLASER 1344088Sbinkertn@umich.edu if (req->getPaddr() & PAddrUncachedBit39) 1353838Shsul@eecs.umich.edu#else 1364088Sbinkertn@umich.edu if (req->getPaddr() & PAddrUncachedBit43) 1373838Shsul@eecs.umich.edu#endif 1384088Sbinkertn@umich.edu { 1393838Shsul@eecs.umich.edu // IPR memory space not implemented 1403838Shsul@eecs.umich.edu if (PAddrIprSpace(req->getPaddr())) { 1413838Shsul@eecs.umich.edu return new UnimpFault("IPR memory space not implemented!"); 1423838Shsul@eecs.umich.edu } else { 1433838Shsul@eecs.umich.edu // mark request as uncacheable 1443838Shsul@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 1453838Shsul@eecs.umich.edu 1463838Shsul@eecs.umich.edu#if !ALPHA_TLASER 1473838Shsul@eecs.umich.edu // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) 1483838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & PAddrUncachedMask); 1493838Shsul@eecs.umich.edu#endif 150924SN/A } 1512SN/A } 1523838Shsul@eecs.umich.edu return NoFault; 1533838Shsul@eecs.umich.edu} 1542SN/A 1552SN/A 1563838Shsul@eecs.umich.edu// insert a new TLB entry 1573838Shsul@eecs.umich.eduvoid 1585004Sgblack@eecs.umich.eduTLB::insert(Addr addr, TlbEntry &entry) 1593838Shsul@eecs.umich.edu{ 1604957Sacolyte@umich.edu flushCache(); 1613838Shsul@eecs.umich.edu VAddr vaddr = addr; 1623838Shsul@eecs.umich.edu if (table[nlu].valid) { 1633838Shsul@eecs.umich.edu Addr oldvpn = table[nlu].tag; 1643838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(oldvpn); 1653838Shsul@eecs.umich.edu 1663838Shsul@eecs.umich.edu if (i == lookupTable.end()) 1673838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 1683838Shsul@eecs.umich.edu 1693838Shsul@eecs.umich.edu int index; 1703838Shsul@eecs.umich.edu while ((index = i->second) != nlu) { 1713838Shsul@eecs.umich.edu if (table[index].tag != oldvpn) 1723838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 1733838Shsul@eecs.umich.edu 1743838Shsul@eecs.umich.edu ++i; 1753838Shsul@eecs.umich.edu } 1763838Shsul@eecs.umich.edu 1773838Shsul@eecs.umich.edu DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 1783838Shsul@eecs.umich.edu 1793838Shsul@eecs.umich.edu lookupTable.erase(i); 1803838Shsul@eecs.umich.edu } 1813838Shsul@eecs.umich.edu 1825004Sgblack@eecs.umich.edu DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn); 1833838Shsul@eecs.umich.edu 1845004Sgblack@eecs.umich.edu table[nlu] = entry; 1853838Shsul@eecs.umich.edu table[nlu].tag = vaddr.vpn(); 1863838Shsul@eecs.umich.edu table[nlu].valid = true; 1873838Shsul@eecs.umich.edu 1883838Shsul@eecs.umich.edu lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 1893838Shsul@eecs.umich.edu nextnlu(); 1903838Shsul@eecs.umich.edu} 1913838Shsul@eecs.umich.edu 1923838Shsul@eecs.umich.eduvoid 1933838Shsul@eecs.umich.eduTLB::flushAll() 1943838Shsul@eecs.umich.edu{ 1953838Shsul@eecs.umich.edu DPRINTF(TLB, "flushAll\n"); 1965004Sgblack@eecs.umich.edu memset(table, 0, sizeof(TlbEntry[size])); 1974957Sacolyte@umich.edu flushCache(); 1983838Shsul@eecs.umich.edu lookupTable.clear(); 1993838Shsul@eecs.umich.edu nlu = 0; 2003838Shsul@eecs.umich.edu} 2013838Shsul@eecs.umich.edu 2023838Shsul@eecs.umich.eduvoid 2033838Shsul@eecs.umich.eduTLB::flushProcesses() 2043838Shsul@eecs.umich.edu{ 2054957Sacolyte@umich.edu flushCache(); 2063838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.begin(); 2073838Shsul@eecs.umich.edu PageTable::iterator end = lookupTable.end(); 2083838Shsul@eecs.umich.edu while (i != end) { 2093838Shsul@eecs.umich.edu int index = i->second; 2105004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 2115004Sgblack@eecs.umich.edu assert(entry->valid); 2123838Shsul@eecs.umich.edu 2133838Shsul@eecs.umich.edu // we can't increment i after we erase it, so save a copy and 2143838Shsul@eecs.umich.edu // increment it to get the next entry now 2153838Shsul@eecs.umich.edu PageTable::iterator cur = i; 2163838Shsul@eecs.umich.edu ++i; 2173838Shsul@eecs.umich.edu 2185004Sgblack@eecs.umich.edu if (!entry->asma) { 2195004Sgblack@eecs.umich.edu DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, entry->tag, entry->ppn); 2205004Sgblack@eecs.umich.edu entry->valid = false; 2213838Shsul@eecs.umich.edu lookupTable.erase(cur); 2223453Sgblack@eecs.umich.edu } 2233453Sgblack@eecs.umich.edu } 2243838Shsul@eecs.umich.edu} 2252SN/A 2263838Shsul@eecs.umich.eduvoid 2273838Shsul@eecs.umich.eduTLB::flushAddr(Addr addr, uint8_t asn) 2283838Shsul@eecs.umich.edu{ 2294957Sacolyte@umich.edu flushCache(); 2303838Shsul@eecs.umich.edu VAddr vaddr = addr; 2312SN/A 2323838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(vaddr.vpn()); 2333838Shsul@eecs.umich.edu if (i == lookupTable.end()) 2343838Shsul@eecs.umich.edu return; 2352SN/A 2364428Ssaidi@eecs.umich.edu while (i != lookupTable.end() && i->first == vaddr.vpn()) { 2373838Shsul@eecs.umich.edu int index = i->second; 2385004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 2395004Sgblack@eecs.umich.edu assert(entry->valid); 2403453Sgblack@eecs.umich.edu 2415004Sgblack@eecs.umich.edu if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) { 2423838Shsul@eecs.umich.edu DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 2435004Sgblack@eecs.umich.edu entry->ppn); 2443453Sgblack@eecs.umich.edu 2453838Shsul@eecs.umich.edu // invalidate this entry 2465004Sgblack@eecs.umich.edu entry->valid = false; 2473838Shsul@eecs.umich.edu 2484428Ssaidi@eecs.umich.edu lookupTable.erase(i++); 2494428Ssaidi@eecs.umich.edu } else { 2504428Ssaidi@eecs.umich.edu ++i; 2513838Shsul@eecs.umich.edu } 2523838Shsul@eecs.umich.edu } 2533838Shsul@eecs.umich.edu} 2543838Shsul@eecs.umich.edu 2553838Shsul@eecs.umich.edu 2563838Shsul@eecs.umich.eduvoid 2573838Shsul@eecs.umich.eduTLB::serialize(ostream &os) 2583838Shsul@eecs.umich.edu{ 2593838Shsul@eecs.umich.edu SERIALIZE_SCALAR(size); 2603838Shsul@eecs.umich.edu SERIALIZE_SCALAR(nlu); 2613838Shsul@eecs.umich.edu 2623838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 2635004Sgblack@eecs.umich.edu nameOut(os, csprintf("%s.Entry%d", name(), i)); 2643838Shsul@eecs.umich.edu table[i].serialize(os); 2653838Shsul@eecs.umich.edu } 2663838Shsul@eecs.umich.edu} 2673838Shsul@eecs.umich.edu 2683838Shsul@eecs.umich.eduvoid 2693838Shsul@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const string §ion) 2703838Shsul@eecs.umich.edu{ 2713838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(size); 2723838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(nlu); 2733838Shsul@eecs.umich.edu 2743838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 2755004Sgblack@eecs.umich.edu table[i].unserialize(cp, csprintf("%s.Entry%d", section, i)); 2763838Shsul@eecs.umich.edu if (table[i].valid) { 2773838Shsul@eecs.umich.edu lookupTable.insert(make_pair(table[i].tag, i)); 2783838Shsul@eecs.umich.edu } 2793838Shsul@eecs.umich.edu } 2803838Shsul@eecs.umich.edu} 2813838Shsul@eecs.umich.edu 2823838Shsul@eecs.umich.edu 2833838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 2843838Shsul@eecs.umich.edu// 2853838Shsul@eecs.umich.edu// Alpha ITB 2863838Shsul@eecs.umich.edu// 2875034Smilesck@eecs.umich.eduITB::ITB(const Params *p) 2885034Smilesck@eecs.umich.edu : TLB(p) 2893838Shsul@eecs.umich.edu{} 2903838Shsul@eecs.umich.edu 2913838Shsul@eecs.umich.edu 2923838Shsul@eecs.umich.eduvoid 2933838Shsul@eecs.umich.eduITB::regStats() 2943838Shsul@eecs.umich.edu{ 2953838Shsul@eecs.umich.edu hits 2963838Shsul@eecs.umich.edu .name(name() + ".hits") 2973838Shsul@eecs.umich.edu .desc("ITB hits"); 2983838Shsul@eecs.umich.edu misses 2993838Shsul@eecs.umich.edu .name(name() + ".misses") 3003838Shsul@eecs.umich.edu .desc("ITB misses"); 3013838Shsul@eecs.umich.edu acv 3023838Shsul@eecs.umich.edu .name(name() + ".acv") 3033838Shsul@eecs.umich.edu .desc("ITB acv"); 3043838Shsul@eecs.umich.edu accesses 3053838Shsul@eecs.umich.edu .name(name() + ".accesses") 3063838Shsul@eecs.umich.edu .desc("ITB accesses"); 3073838Shsul@eecs.umich.edu 3083838Shsul@eecs.umich.edu accesses = hits + misses; 3093838Shsul@eecs.umich.edu} 3103838Shsul@eecs.umich.edu 3113838Shsul@eecs.umich.edu 3123838Shsul@eecs.umich.eduFault 3134967Sacolyte@umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 3143838Shsul@eecs.umich.edu{ 3154375Sgblack@eecs.umich.edu //If this is a pal pc, then set PHYSICAL 3164375Sgblack@eecs.umich.edu if(FULL_SYSTEM && PcPAL(req->getPC())) 3174375Sgblack@eecs.umich.edu req->setFlags(req->getFlags() | PHYSICAL); 3184375Sgblack@eecs.umich.edu 3193838Shsul@eecs.umich.edu if (PcPAL(req->getPC())) { 3203838Shsul@eecs.umich.edu // strip off PAL PC marker (lsb is 1) 3213838Shsul@eecs.umich.edu req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 3223838Shsul@eecs.umich.edu hits++; 3233838Shsul@eecs.umich.edu return NoFault; 3243453Sgblack@eecs.umich.edu } 3253453Sgblack@eecs.umich.edu 3263838Shsul@eecs.umich.edu if (req->getFlags() & PHYSICAL) { 3273838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 3283838Shsul@eecs.umich.edu } else { 3293838Shsul@eecs.umich.edu // verify that this is a good virtual address 3303838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 3313838Shsul@eecs.umich.edu acv++; 3323838Shsul@eecs.umich.edu return new ItbAcvFault(req->getVaddr()); 3332SN/A } 3342SN/A 3353838Shsul@eecs.umich.edu 3363838Shsul@eecs.umich.edu // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 3373838Shsul@eecs.umich.edu // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 3383838Shsul@eecs.umich.edu#if ALPHA_TLASER 3394172Ssaidi@eecs.umich.edu if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 3404088Sbinkertn@umich.edu VAddrSpaceEV5(req->getVaddr()) == 2) 3413838Shsul@eecs.umich.edu#else 3424088Sbinkertn@umich.edu if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 3433838Shsul@eecs.umich.edu#endif 3444088Sbinkertn@umich.edu { 3453838Shsul@eecs.umich.edu // only valid in kernel mode 3464172Ssaidi@eecs.umich.edu if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 3473838Shsul@eecs.umich.edu mode_kernel) { 348555SN/A acv++; 3492532SN/A return new ItbAcvFault(req->getVaddr()); 350555SN/A } 3512SN/A 3523838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 353551SN/A 3541858SN/A#if !ALPHA_TLASER 3553838Shsul@eecs.umich.edu // sign extend the physical address properly 3563838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 3573838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 3583838Shsul@eecs.umich.edu else 3593838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 360924SN/A#endif 361828SN/A 3623838Shsul@eecs.umich.edu } else { 3633838Shsul@eecs.umich.edu // not a physical address: need to look up pte 3644172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 3655004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), 3663838Shsul@eecs.umich.edu asn); 3673838Shsul@eecs.umich.edu 3685004Sgblack@eecs.umich.edu if (!entry) { 3693838Shsul@eecs.umich.edu misses++; 3703838Shsul@eecs.umich.edu return new ItbPageFault(req->getVaddr()); 3713838Shsul@eecs.umich.edu } 3723838Shsul@eecs.umich.edu 3735004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 3743838Shsul@eecs.umich.edu (VAddr(req->getVaddr()).offset() 3753838Shsul@eecs.umich.edu & ~3)); 3763838Shsul@eecs.umich.edu 3773838Shsul@eecs.umich.edu // check permissions for this access 3785004Sgblack@eecs.umich.edu if (!(entry->xre & 3794172Ssaidi@eecs.umich.edu (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { 3803838Shsul@eecs.umich.edu // instruction access fault 3813838Shsul@eecs.umich.edu acv++; 3823838Shsul@eecs.umich.edu return new ItbAcvFault(req->getVaddr()); 3833838Shsul@eecs.umich.edu } 3843838Shsul@eecs.umich.edu 3853838Shsul@eecs.umich.edu hits++; 3863838Shsul@eecs.umich.edu } 3873838Shsul@eecs.umich.edu } 3883838Shsul@eecs.umich.edu 3893838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 3903838Shsul@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) 3913838Shsul@eecs.umich.edu return genMachineCheckFault(); 3923838Shsul@eecs.umich.edu 3933838Shsul@eecs.umich.edu return checkCacheability(req); 3943838Shsul@eecs.umich.edu 3953838Shsul@eecs.umich.edu} 3963838Shsul@eecs.umich.edu 3973838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 3983838Shsul@eecs.umich.edu// 3993838Shsul@eecs.umich.edu// Alpha DTB 4003838Shsul@eecs.umich.edu// 4015034Smilesck@eecs.umich.edu DTB::DTB(const Params *p) 4025034Smilesck@eecs.umich.edu : TLB(p) 4033838Shsul@eecs.umich.edu{} 4043838Shsul@eecs.umich.edu 4053838Shsul@eecs.umich.eduvoid 4063838Shsul@eecs.umich.eduDTB::regStats() 4073838Shsul@eecs.umich.edu{ 4083838Shsul@eecs.umich.edu read_hits 4093838Shsul@eecs.umich.edu .name(name() + ".read_hits") 4103838Shsul@eecs.umich.edu .desc("DTB read hits") 4113838Shsul@eecs.umich.edu ; 4123838Shsul@eecs.umich.edu 4133838Shsul@eecs.umich.edu read_misses 4143838Shsul@eecs.umich.edu .name(name() + ".read_misses") 4153838Shsul@eecs.umich.edu .desc("DTB read misses") 4163838Shsul@eecs.umich.edu ; 4173838Shsul@eecs.umich.edu 4183838Shsul@eecs.umich.edu read_acv 4193838Shsul@eecs.umich.edu .name(name() + ".read_acv") 4203838Shsul@eecs.umich.edu .desc("DTB read access violations") 4213838Shsul@eecs.umich.edu ; 4223838Shsul@eecs.umich.edu 4233838Shsul@eecs.umich.edu read_accesses 4243838Shsul@eecs.umich.edu .name(name() + ".read_accesses") 4253838Shsul@eecs.umich.edu .desc("DTB read accesses") 4263838Shsul@eecs.umich.edu ; 4273838Shsul@eecs.umich.edu 4283838Shsul@eecs.umich.edu write_hits 4293838Shsul@eecs.umich.edu .name(name() + ".write_hits") 4303838Shsul@eecs.umich.edu .desc("DTB write hits") 4313838Shsul@eecs.umich.edu ; 4323838Shsul@eecs.umich.edu 4333838Shsul@eecs.umich.edu write_misses 4343838Shsul@eecs.umich.edu .name(name() + ".write_misses") 4353838Shsul@eecs.umich.edu .desc("DTB write misses") 4363838Shsul@eecs.umich.edu ; 4373838Shsul@eecs.umich.edu 4383838Shsul@eecs.umich.edu write_acv 4393838Shsul@eecs.umich.edu .name(name() + ".write_acv") 4403838Shsul@eecs.umich.edu .desc("DTB write access violations") 4413838Shsul@eecs.umich.edu ; 4423838Shsul@eecs.umich.edu 4433838Shsul@eecs.umich.edu write_accesses 4443838Shsul@eecs.umich.edu .name(name() + ".write_accesses") 4453838Shsul@eecs.umich.edu .desc("DTB write accesses") 4463838Shsul@eecs.umich.edu ; 4473838Shsul@eecs.umich.edu 4483838Shsul@eecs.umich.edu hits 4493838Shsul@eecs.umich.edu .name(name() + ".hits") 4503838Shsul@eecs.umich.edu .desc("DTB hits") 4513838Shsul@eecs.umich.edu ; 4523838Shsul@eecs.umich.edu 4533838Shsul@eecs.umich.edu misses 4543838Shsul@eecs.umich.edu .name(name() + ".misses") 4553838Shsul@eecs.umich.edu .desc("DTB misses") 4563838Shsul@eecs.umich.edu ; 4573838Shsul@eecs.umich.edu 4583838Shsul@eecs.umich.edu acv 4593838Shsul@eecs.umich.edu .name(name() + ".acv") 4603838Shsul@eecs.umich.edu .desc("DTB access violations") 4613838Shsul@eecs.umich.edu ; 4623838Shsul@eecs.umich.edu 4633838Shsul@eecs.umich.edu accesses 4643838Shsul@eecs.umich.edu .name(name() + ".accesses") 4653838Shsul@eecs.umich.edu .desc("DTB accesses") 4663838Shsul@eecs.umich.edu ; 4673838Shsul@eecs.umich.edu 4683838Shsul@eecs.umich.edu hits = read_hits + write_hits; 4693838Shsul@eecs.umich.edu misses = read_misses + write_misses; 4703838Shsul@eecs.umich.edu acv = read_acv + write_acv; 4713838Shsul@eecs.umich.edu accesses = read_accesses + write_accesses; 4723838Shsul@eecs.umich.edu} 4733838Shsul@eecs.umich.edu 4743838Shsul@eecs.umich.eduFault 4754967Sacolyte@umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 4763838Shsul@eecs.umich.edu{ 4773838Shsul@eecs.umich.edu Addr pc = tc->readPC(); 4783838Shsul@eecs.umich.edu 4793838Shsul@eecs.umich.edu mode_type mode = 4804172Ssaidi@eecs.umich.edu (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 4813838Shsul@eecs.umich.edu 4823838Shsul@eecs.umich.edu 4833838Shsul@eecs.umich.edu /** 4843838Shsul@eecs.umich.edu * Check for alignment faults 4853838Shsul@eecs.umich.edu */ 4863838Shsul@eecs.umich.edu if (req->getVaddr() & (req->getSize() - 1)) { 4873838Shsul@eecs.umich.edu DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 4883838Shsul@eecs.umich.edu req->getSize()); 4893838Shsul@eecs.umich.edu uint64_t flags = write ? MM_STAT_WR_MASK : 0; 4903838Shsul@eecs.umich.edu return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); 4913838Shsul@eecs.umich.edu } 4923838Shsul@eecs.umich.edu 4933838Shsul@eecs.umich.edu if (PcPAL(pc)) { 4943838Shsul@eecs.umich.edu mode = (req->getFlags() & ALTMODE) ? 4953838Shsul@eecs.umich.edu (mode_type)ALT_MODE_AM( 4964172Ssaidi@eecs.umich.edu tc->readMiscRegNoEffect(IPR_ALT_MODE)) 4973838Shsul@eecs.umich.edu : mode_kernel; 4983838Shsul@eecs.umich.edu } 4993838Shsul@eecs.umich.edu 5003838Shsul@eecs.umich.edu if (req->getFlags() & PHYSICAL) { 5013838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 5023838Shsul@eecs.umich.edu } else { 5033838Shsul@eecs.umich.edu // verify that this is a good virtual address 5043838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 5053838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 5063838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 5073838Shsul@eecs.umich.edu MM_STAT_BAD_VA_MASK | 5083838Shsul@eecs.umich.edu MM_STAT_ACV_MASK; 5093838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 5103838Shsul@eecs.umich.edu } 5113838Shsul@eecs.umich.edu 5123838Shsul@eecs.umich.edu // Check for "superpage" mapping 5133838Shsul@eecs.umich.edu#if ALPHA_TLASER 5144172Ssaidi@eecs.umich.edu if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 5154088Sbinkertn@umich.edu VAddrSpaceEV5(req->getVaddr()) == 2) 5163838Shsul@eecs.umich.edu#else 5174088Sbinkertn@umich.edu if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 5183838Shsul@eecs.umich.edu#endif 5194088Sbinkertn@umich.edu { 5203838Shsul@eecs.umich.edu 5213838Shsul@eecs.umich.edu // only valid in kernel mode 5224172Ssaidi@eecs.umich.edu if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 5233838Shsul@eecs.umich.edu mode_kernel) { 5243838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 5253838Shsul@eecs.umich.edu uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 5263838Shsul@eecs.umich.edu MM_STAT_ACV_MASK); 5273838Shsul@eecs.umich.edu return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 5283838Shsul@eecs.umich.edu } 5293838Shsul@eecs.umich.edu 5303838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 5313838Shsul@eecs.umich.edu 5323838Shsul@eecs.umich.edu#if !ALPHA_TLASER 5333838Shsul@eecs.umich.edu // sign extend the physical address properly 5343838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 5353838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 5363838Shsul@eecs.umich.edu else 5373838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 5383838Shsul@eecs.umich.edu#endif 5393838Shsul@eecs.umich.edu 5403838Shsul@eecs.umich.edu } else { 5413838Shsul@eecs.umich.edu if (write) 5423838Shsul@eecs.umich.edu write_accesses++; 5433838Shsul@eecs.umich.edu else 5443838Shsul@eecs.umich.edu read_accesses++; 5453838Shsul@eecs.umich.edu 5464172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 5473838Shsul@eecs.umich.edu 5483838Shsul@eecs.umich.edu // not a physical address: need to look up pte 5495004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn); 5503838Shsul@eecs.umich.edu 5515004Sgblack@eecs.umich.edu if (!entry) { 5523838Shsul@eecs.umich.edu // page fault 5533838Shsul@eecs.umich.edu if (write) { write_misses++; } else { read_misses++; } 5543838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 5553838Shsul@eecs.umich.edu MM_STAT_DTB_MISS_MASK; 5563838Shsul@eecs.umich.edu return (req->getFlags() & VPTE) ? 5573838Shsul@eecs.umich.edu (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), 5583838Shsul@eecs.umich.edu flags)) : 5593838Shsul@eecs.umich.edu (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), 5603838Shsul@eecs.umich.edu flags)); 5613838Shsul@eecs.umich.edu } 5623838Shsul@eecs.umich.edu 5635004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 5643838Shsul@eecs.umich.edu VAddr(req->getVaddr()).offset()); 5653838Shsul@eecs.umich.edu 5663838Shsul@eecs.umich.edu if (write) { 5675004Sgblack@eecs.umich.edu if (!(entry->xwe & MODE2MASK(mode))) { 5683838Shsul@eecs.umich.edu // declare the instruction access fault 5693838Shsul@eecs.umich.edu write_acv++; 5703838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_WR_MASK | 5713838Shsul@eecs.umich.edu MM_STAT_ACV_MASK | 5725004Sgblack@eecs.umich.edu (entry->fonw ? MM_STAT_FONW_MASK : 0); 5733838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 5743838Shsul@eecs.umich.edu } 5755004Sgblack@eecs.umich.edu if (entry->fonw) { 5763838Shsul@eecs.umich.edu write_acv++; 5773838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_WR_MASK | 5783838Shsul@eecs.umich.edu MM_STAT_FONW_MASK; 5793838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 5803838Shsul@eecs.umich.edu } 5813453Sgblack@eecs.umich.edu } else { 5825004Sgblack@eecs.umich.edu if (!(entry->xre & MODE2MASK(mode))) { 5833838Shsul@eecs.umich.edu read_acv++; 5843838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_ACV_MASK | 5855004Sgblack@eecs.umich.edu (entry->fonr ? MM_STAT_FONR_MASK : 0); 5863838Shsul@eecs.umich.edu return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 5873453Sgblack@eecs.umich.edu } 5885004Sgblack@eecs.umich.edu if (entry->fonr) { 5893838Shsul@eecs.umich.edu read_acv++; 5903838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_FONR_MASK; 5913838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 5923453Sgblack@eecs.umich.edu } 5932SN/A } 5942SN/A } 595551SN/A 5963838Shsul@eecs.umich.edu if (write) 5973838Shsul@eecs.umich.edu write_hits++; 5983838Shsul@eecs.umich.edu else 5993838Shsul@eecs.umich.edu read_hits++; 6002SN/A } 6012SN/A 6023838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 6033838Shsul@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) 6043838Shsul@eecs.umich.edu return genMachineCheckFault(); 605551SN/A 6063838Shsul@eecs.umich.edu return checkCacheability(req); 6073838Shsul@eecs.umich.edu} 6083453Sgblack@eecs.umich.edu 6095004Sgblack@eecs.umich.eduTlbEntry & 6103838Shsul@eecs.umich.eduTLB::index(bool advance) 6113838Shsul@eecs.umich.edu{ 6125004Sgblack@eecs.umich.edu TlbEntry *entry = &table[nlu]; 6133453Sgblack@eecs.umich.edu 6143838Shsul@eecs.umich.edu if (advance) 6153838Shsul@eecs.umich.edu nextnlu(); 6163453Sgblack@eecs.umich.edu 6175004Sgblack@eecs.umich.edu return *entry; 6183838Shsul@eecs.umich.edu} 6193453Sgblack@eecs.umich.edu 6204088Sbinkertn@umich.edu/* end namespace AlphaISA */ } 6214088Sbinkertn@umich.edu 6224762Snate@binkert.orgAlphaISA::ITB * 6234762Snate@binkert.orgAlphaITBParams::create() 6243838Shsul@eecs.umich.edu{ 6255034Smilesck@eecs.umich.edu return new AlphaISA::ITB(this); 6263838Shsul@eecs.umich.edu} 6273453Sgblack@eecs.umich.edu 6284762Snate@binkert.orgAlphaISA::DTB * 6294762Snate@binkert.orgAlphaDTBParams::create() 6303838Shsul@eecs.umich.edu{ 6315034Smilesck@eecs.umich.edu return new AlphaISA::DTB(this); 6323838Shsul@eecs.umich.edu} 633