tlb.cc revision 4375
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Andrew Schultz 312SN/A */ 322SN/A 332SN/A#include <string> 342SN/A#include <vector> 352SN/A 362984Sgblack@eecs.umich.edu#include "arch/alpha/pagetable.hh" 372171SN/A#include "arch/alpha/tlb.hh" 382984Sgblack@eecs.umich.edu#include "arch/alpha/faults.hh" 39146SN/A#include "base/inifile.hh" 40146SN/A#include "base/str.hh" 41146SN/A#include "base/trace.hh" 421858SN/A#include "config/alpha_tlaser.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 44146SN/A#include "sim/builder.hh" 452SN/A 462SN/Ausing namespace std; 471147SN/Ausing namespace EV5; 482SN/A 494088Sbinkertn@umich.edunamespace AlphaISA { 503838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 513838Shsul@eecs.umich.edu// 523838Shsul@eecs.umich.edu// Alpha TLB 533838Shsul@eecs.umich.edu// 54860SN/A#ifdef DEBUG 553838Shsul@eecs.umich.edubool uncacheBit39 = false; 563838Shsul@eecs.umich.edubool uncacheBit40 = false; 57860SN/A#endif 58860SN/A 591147SN/A#define MODE2MASK(X) (1 << (X)) 601147SN/A 613838Shsul@eecs.umich.eduTLB::TLB(const string &name, int s) 623838Shsul@eecs.umich.edu : SimObject(name), size(s), nlu(0) 633838Shsul@eecs.umich.edu{ 643838Shsul@eecs.umich.edu table = new PTE[size]; 653838Shsul@eecs.umich.edu memset(table, 0, sizeof(PTE[size])); 663838Shsul@eecs.umich.edu} 672SN/A 683838Shsul@eecs.umich.eduTLB::~TLB() 693838Shsul@eecs.umich.edu{ 703838Shsul@eecs.umich.edu if (table) 713838Shsul@eecs.umich.edu delete [] table; 723838Shsul@eecs.umich.edu} 732SN/A 743838Shsul@eecs.umich.edu// look up an entry in the TLB 753838Shsul@eecs.umich.eduPTE * 763838Shsul@eecs.umich.eduTLB::lookup(Addr vpn, uint8_t asn) const 773838Shsul@eecs.umich.edu{ 783838Shsul@eecs.umich.edu // assume not found... 793838Shsul@eecs.umich.edu PTE *retval = NULL; 802SN/A 813838Shsul@eecs.umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 823838Shsul@eecs.umich.edu if (i != lookupTable.end()) { 833838Shsul@eecs.umich.edu while (i->first == vpn) { 841413SN/A int index = i->second; 853453Sgblack@eecs.umich.edu PTE *pte = &table[index]; 861413SN/A assert(pte->valid); 873838Shsul@eecs.umich.edu if (vpn == pte->tag && (pte->asma || pte->asn == asn)) { 883838Shsul@eecs.umich.edu retval = pte; 893838Shsul@eecs.umich.edu break; 901413SN/A } 912SN/A 921413SN/A ++i; 931413SN/A } 942SN/A } 952SN/A 963838Shsul@eecs.umich.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 973838Shsul@eecs.umich.edu retval ? "hit" : "miss", retval ? retval->ppn : 0); 983838Shsul@eecs.umich.edu return retval; 993838Shsul@eecs.umich.edu} 1002SN/A 1012SN/A 1023838Shsul@eecs.umich.eduFault 1033838Shsul@eecs.umich.eduTLB::checkCacheability(RequestPtr &req) 1043838Shsul@eecs.umich.edu{ 1053838Shsul@eecs.umich.edu// in Alpha, cacheability is controlled by upper-level bits of the 1063838Shsul@eecs.umich.edu// physical address 1073838Shsul@eecs.umich.edu 1083838Shsul@eecs.umich.edu/* 1093838Shsul@eecs.umich.edu * We support having the uncacheable bit in either bit 39 or bit 40. 1103838Shsul@eecs.umich.edu * The Turbolaser platform (and EV5) support having the bit in 39, but 1113838Shsul@eecs.umich.edu * Tsunami (which Linux assumes uses an EV6) generates accesses with 1123838Shsul@eecs.umich.edu * the bit in 40. So we must check for both, but we have debug flags 1133838Shsul@eecs.umich.edu * to catch a weird case where both are used, which shouldn't happen. 1143838Shsul@eecs.umich.edu */ 1153838Shsul@eecs.umich.edu 1163838Shsul@eecs.umich.edu 1173838Shsul@eecs.umich.edu#if ALPHA_TLASER 1184088Sbinkertn@umich.edu if (req->getPaddr() & PAddrUncachedBit39) 1193838Shsul@eecs.umich.edu#else 1204088Sbinkertn@umich.edu if (req->getPaddr() & PAddrUncachedBit43) 1213838Shsul@eecs.umich.edu#endif 1224088Sbinkertn@umich.edu { 1233838Shsul@eecs.umich.edu // IPR memory space not implemented 1243838Shsul@eecs.umich.edu if (PAddrIprSpace(req->getPaddr())) { 1253838Shsul@eecs.umich.edu return new UnimpFault("IPR memory space not implemented!"); 1263838Shsul@eecs.umich.edu } else { 1273838Shsul@eecs.umich.edu // mark request as uncacheable 1283838Shsul@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 1293838Shsul@eecs.umich.edu 1303838Shsul@eecs.umich.edu#if !ALPHA_TLASER 1313838Shsul@eecs.umich.edu // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) 1323838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & PAddrUncachedMask); 1333838Shsul@eecs.umich.edu#endif 134924SN/A } 1352SN/A } 1363838Shsul@eecs.umich.edu return NoFault; 1373838Shsul@eecs.umich.edu} 1382SN/A 1392SN/A 1403838Shsul@eecs.umich.edu// insert a new TLB entry 1413838Shsul@eecs.umich.eduvoid 1423838Shsul@eecs.umich.eduTLB::insert(Addr addr, PTE &pte) 1433838Shsul@eecs.umich.edu{ 1443838Shsul@eecs.umich.edu VAddr vaddr = addr; 1453838Shsul@eecs.umich.edu if (table[nlu].valid) { 1463838Shsul@eecs.umich.edu Addr oldvpn = table[nlu].tag; 1473838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(oldvpn); 1483838Shsul@eecs.umich.edu 1493838Shsul@eecs.umich.edu if (i == lookupTable.end()) 1503838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 1513838Shsul@eecs.umich.edu 1523838Shsul@eecs.umich.edu int index; 1533838Shsul@eecs.umich.edu while ((index = i->second) != nlu) { 1543838Shsul@eecs.umich.edu if (table[index].tag != oldvpn) 1553838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 1563838Shsul@eecs.umich.edu 1573838Shsul@eecs.umich.edu ++i; 1583838Shsul@eecs.umich.edu } 1593838Shsul@eecs.umich.edu 1603838Shsul@eecs.umich.edu DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 1613838Shsul@eecs.umich.edu 1623838Shsul@eecs.umich.edu lookupTable.erase(i); 1633838Shsul@eecs.umich.edu } 1643838Shsul@eecs.umich.edu 1653838Shsul@eecs.umich.edu DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn); 1663838Shsul@eecs.umich.edu 1673838Shsul@eecs.umich.edu table[nlu] = pte; 1683838Shsul@eecs.umich.edu table[nlu].tag = vaddr.vpn(); 1693838Shsul@eecs.umich.edu table[nlu].valid = true; 1703838Shsul@eecs.umich.edu 1713838Shsul@eecs.umich.edu lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 1723838Shsul@eecs.umich.edu nextnlu(); 1733838Shsul@eecs.umich.edu} 1743838Shsul@eecs.umich.edu 1753838Shsul@eecs.umich.eduvoid 1763838Shsul@eecs.umich.eduTLB::flushAll() 1773838Shsul@eecs.umich.edu{ 1783838Shsul@eecs.umich.edu DPRINTF(TLB, "flushAll\n"); 1793838Shsul@eecs.umich.edu memset(table, 0, sizeof(PTE[size])); 1803838Shsul@eecs.umich.edu lookupTable.clear(); 1813838Shsul@eecs.umich.edu nlu = 0; 1823838Shsul@eecs.umich.edu} 1833838Shsul@eecs.umich.edu 1843838Shsul@eecs.umich.eduvoid 1853838Shsul@eecs.umich.eduTLB::flushProcesses() 1863838Shsul@eecs.umich.edu{ 1873838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.begin(); 1883838Shsul@eecs.umich.edu PageTable::iterator end = lookupTable.end(); 1893838Shsul@eecs.umich.edu while (i != end) { 1903838Shsul@eecs.umich.edu int index = i->second; 1913838Shsul@eecs.umich.edu PTE *pte = &table[index]; 1923838Shsul@eecs.umich.edu assert(pte->valid); 1933838Shsul@eecs.umich.edu 1943838Shsul@eecs.umich.edu // we can't increment i after we erase it, so save a copy and 1953838Shsul@eecs.umich.edu // increment it to get the next entry now 1963838Shsul@eecs.umich.edu PageTable::iterator cur = i; 1973838Shsul@eecs.umich.edu ++i; 1983838Shsul@eecs.umich.edu 1993838Shsul@eecs.umich.edu if (!pte->asma) { 2003838Shsul@eecs.umich.edu DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn); 2013838Shsul@eecs.umich.edu pte->valid = false; 2023838Shsul@eecs.umich.edu lookupTable.erase(cur); 2033453Sgblack@eecs.umich.edu } 2043453Sgblack@eecs.umich.edu } 2053838Shsul@eecs.umich.edu} 2062SN/A 2073838Shsul@eecs.umich.eduvoid 2083838Shsul@eecs.umich.eduTLB::flushAddr(Addr addr, uint8_t asn) 2093838Shsul@eecs.umich.edu{ 2103838Shsul@eecs.umich.edu VAddr vaddr = addr; 2112SN/A 2123838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(vaddr.vpn()); 2133838Shsul@eecs.umich.edu if (i == lookupTable.end()) 2143838Shsul@eecs.umich.edu return; 2152SN/A 2163838Shsul@eecs.umich.edu while (i->first == vaddr.vpn()) { 2173838Shsul@eecs.umich.edu int index = i->second; 2183838Shsul@eecs.umich.edu PTE *pte = &table[index]; 2193838Shsul@eecs.umich.edu assert(pte->valid); 2203453Sgblack@eecs.umich.edu 2213838Shsul@eecs.umich.edu if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) { 2223838Shsul@eecs.umich.edu DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 2233838Shsul@eecs.umich.edu pte->ppn); 2243453Sgblack@eecs.umich.edu 2253838Shsul@eecs.umich.edu // invalidate this entry 2263838Shsul@eecs.umich.edu pte->valid = false; 2273838Shsul@eecs.umich.edu 2283838Shsul@eecs.umich.edu lookupTable.erase(i); 2293838Shsul@eecs.umich.edu } 2303838Shsul@eecs.umich.edu 2313838Shsul@eecs.umich.edu ++i; 2323838Shsul@eecs.umich.edu } 2333838Shsul@eecs.umich.edu} 2343838Shsul@eecs.umich.edu 2353838Shsul@eecs.umich.edu 2363838Shsul@eecs.umich.eduvoid 2373838Shsul@eecs.umich.eduTLB::serialize(ostream &os) 2383838Shsul@eecs.umich.edu{ 2393838Shsul@eecs.umich.edu SERIALIZE_SCALAR(size); 2403838Shsul@eecs.umich.edu SERIALIZE_SCALAR(nlu); 2413838Shsul@eecs.umich.edu 2423838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 2433838Shsul@eecs.umich.edu nameOut(os, csprintf("%s.PTE%d", name(), i)); 2443838Shsul@eecs.umich.edu table[i].serialize(os); 2453838Shsul@eecs.umich.edu } 2463838Shsul@eecs.umich.edu} 2473838Shsul@eecs.umich.edu 2483838Shsul@eecs.umich.eduvoid 2493838Shsul@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const string §ion) 2503838Shsul@eecs.umich.edu{ 2513838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(size); 2523838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(nlu); 2533838Shsul@eecs.umich.edu 2543838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 2553838Shsul@eecs.umich.edu table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 2563838Shsul@eecs.umich.edu if (table[i].valid) { 2573838Shsul@eecs.umich.edu lookupTable.insert(make_pair(table[i].tag, i)); 2583838Shsul@eecs.umich.edu } 2593838Shsul@eecs.umich.edu } 2603838Shsul@eecs.umich.edu} 2613838Shsul@eecs.umich.edu 2623838Shsul@eecs.umich.edu 2633838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 2643838Shsul@eecs.umich.edu// 2653838Shsul@eecs.umich.edu// Alpha ITB 2663838Shsul@eecs.umich.edu// 2673838Shsul@eecs.umich.eduITB::ITB(const std::string &name, int size) 2683838Shsul@eecs.umich.edu : TLB(name, size) 2693838Shsul@eecs.umich.edu{} 2703838Shsul@eecs.umich.edu 2713838Shsul@eecs.umich.edu 2723838Shsul@eecs.umich.eduvoid 2733838Shsul@eecs.umich.eduITB::regStats() 2743838Shsul@eecs.umich.edu{ 2753838Shsul@eecs.umich.edu hits 2763838Shsul@eecs.umich.edu .name(name() + ".hits") 2773838Shsul@eecs.umich.edu .desc("ITB hits"); 2783838Shsul@eecs.umich.edu misses 2793838Shsul@eecs.umich.edu .name(name() + ".misses") 2803838Shsul@eecs.umich.edu .desc("ITB misses"); 2813838Shsul@eecs.umich.edu acv 2823838Shsul@eecs.umich.edu .name(name() + ".acv") 2833838Shsul@eecs.umich.edu .desc("ITB acv"); 2843838Shsul@eecs.umich.edu accesses 2853838Shsul@eecs.umich.edu .name(name() + ".accesses") 2863838Shsul@eecs.umich.edu .desc("ITB accesses"); 2873838Shsul@eecs.umich.edu 2883838Shsul@eecs.umich.edu accesses = hits + misses; 2893838Shsul@eecs.umich.edu} 2903838Shsul@eecs.umich.edu 2913838Shsul@eecs.umich.edu 2923838Shsul@eecs.umich.eduFault 2933838Shsul@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) const 2943838Shsul@eecs.umich.edu{ 2954375Sgblack@eecs.umich.edu //If this is a pal pc, then set PHYSICAL 2964375Sgblack@eecs.umich.edu if(FULL_SYSTEM && PcPAL(req->getPC())) 2974375Sgblack@eecs.umich.edu req->setFlags(req->getFlags() | PHYSICAL); 2984375Sgblack@eecs.umich.edu 2993838Shsul@eecs.umich.edu if (PcPAL(req->getPC())) { 3003838Shsul@eecs.umich.edu // strip off PAL PC marker (lsb is 1) 3013838Shsul@eecs.umich.edu req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 3023838Shsul@eecs.umich.edu hits++; 3033838Shsul@eecs.umich.edu return NoFault; 3043453Sgblack@eecs.umich.edu } 3053453Sgblack@eecs.umich.edu 3063838Shsul@eecs.umich.edu if (req->getFlags() & PHYSICAL) { 3073838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 3083838Shsul@eecs.umich.edu } else { 3093838Shsul@eecs.umich.edu // verify that this is a good virtual address 3103838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 3113838Shsul@eecs.umich.edu acv++; 3123838Shsul@eecs.umich.edu return new ItbAcvFault(req->getVaddr()); 3132SN/A } 3142SN/A 3153838Shsul@eecs.umich.edu 3163838Shsul@eecs.umich.edu // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 3173838Shsul@eecs.umich.edu // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 3183838Shsul@eecs.umich.edu#if ALPHA_TLASER 3194172Ssaidi@eecs.umich.edu if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 3204088Sbinkertn@umich.edu VAddrSpaceEV5(req->getVaddr()) == 2) 3213838Shsul@eecs.umich.edu#else 3224088Sbinkertn@umich.edu if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 3233838Shsul@eecs.umich.edu#endif 3244088Sbinkertn@umich.edu { 3253838Shsul@eecs.umich.edu // only valid in kernel mode 3264172Ssaidi@eecs.umich.edu if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 3273838Shsul@eecs.umich.edu mode_kernel) { 328555SN/A acv++; 3292532SN/A return new ItbAcvFault(req->getVaddr()); 330555SN/A } 3312SN/A 3323838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 333551SN/A 3341858SN/A#if !ALPHA_TLASER 3353838Shsul@eecs.umich.edu // sign extend the physical address properly 3363838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 3373838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 3383838Shsul@eecs.umich.edu else 3393838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 340924SN/A#endif 341828SN/A 3423838Shsul@eecs.umich.edu } else { 3433838Shsul@eecs.umich.edu // not a physical address: need to look up pte 3444172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 3453838Shsul@eecs.umich.edu PTE *pte = lookup(VAddr(req->getVaddr()).vpn(), 3463838Shsul@eecs.umich.edu asn); 3473838Shsul@eecs.umich.edu 3483838Shsul@eecs.umich.edu if (!pte) { 3493838Shsul@eecs.umich.edu misses++; 3503838Shsul@eecs.umich.edu return new ItbPageFault(req->getVaddr()); 3513838Shsul@eecs.umich.edu } 3523838Shsul@eecs.umich.edu 3533838Shsul@eecs.umich.edu req->setPaddr((pte->ppn << PageShift) + 3543838Shsul@eecs.umich.edu (VAddr(req->getVaddr()).offset() 3553838Shsul@eecs.umich.edu & ~3)); 3563838Shsul@eecs.umich.edu 3573838Shsul@eecs.umich.edu // check permissions for this access 3583838Shsul@eecs.umich.edu if (!(pte->xre & 3594172Ssaidi@eecs.umich.edu (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { 3603838Shsul@eecs.umich.edu // instruction access fault 3613838Shsul@eecs.umich.edu acv++; 3623838Shsul@eecs.umich.edu return new ItbAcvFault(req->getVaddr()); 3633838Shsul@eecs.umich.edu } 3643838Shsul@eecs.umich.edu 3653838Shsul@eecs.umich.edu hits++; 3663838Shsul@eecs.umich.edu } 3673838Shsul@eecs.umich.edu } 3683838Shsul@eecs.umich.edu 3693838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 3703838Shsul@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) 3713838Shsul@eecs.umich.edu return genMachineCheckFault(); 3723838Shsul@eecs.umich.edu 3733838Shsul@eecs.umich.edu return checkCacheability(req); 3743838Shsul@eecs.umich.edu 3753838Shsul@eecs.umich.edu} 3763838Shsul@eecs.umich.edu 3773838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 3783838Shsul@eecs.umich.edu// 3793838Shsul@eecs.umich.edu// Alpha DTB 3803838Shsul@eecs.umich.edu// 3813838Shsul@eecs.umich.edu DTB::DTB(const std::string &name, int size) 3823838Shsul@eecs.umich.edu : TLB(name, size) 3833838Shsul@eecs.umich.edu{} 3843838Shsul@eecs.umich.edu 3853838Shsul@eecs.umich.eduvoid 3863838Shsul@eecs.umich.eduDTB::regStats() 3873838Shsul@eecs.umich.edu{ 3883838Shsul@eecs.umich.edu read_hits 3893838Shsul@eecs.umich.edu .name(name() + ".read_hits") 3903838Shsul@eecs.umich.edu .desc("DTB read hits") 3913838Shsul@eecs.umich.edu ; 3923838Shsul@eecs.umich.edu 3933838Shsul@eecs.umich.edu read_misses 3943838Shsul@eecs.umich.edu .name(name() + ".read_misses") 3953838Shsul@eecs.umich.edu .desc("DTB read misses") 3963838Shsul@eecs.umich.edu ; 3973838Shsul@eecs.umich.edu 3983838Shsul@eecs.umich.edu read_acv 3993838Shsul@eecs.umich.edu .name(name() + ".read_acv") 4003838Shsul@eecs.umich.edu .desc("DTB read access violations") 4013838Shsul@eecs.umich.edu ; 4023838Shsul@eecs.umich.edu 4033838Shsul@eecs.umich.edu read_accesses 4043838Shsul@eecs.umich.edu .name(name() + ".read_accesses") 4053838Shsul@eecs.umich.edu .desc("DTB read accesses") 4063838Shsul@eecs.umich.edu ; 4073838Shsul@eecs.umich.edu 4083838Shsul@eecs.umich.edu write_hits 4093838Shsul@eecs.umich.edu .name(name() + ".write_hits") 4103838Shsul@eecs.umich.edu .desc("DTB write hits") 4113838Shsul@eecs.umich.edu ; 4123838Shsul@eecs.umich.edu 4133838Shsul@eecs.umich.edu write_misses 4143838Shsul@eecs.umich.edu .name(name() + ".write_misses") 4153838Shsul@eecs.umich.edu .desc("DTB write misses") 4163838Shsul@eecs.umich.edu ; 4173838Shsul@eecs.umich.edu 4183838Shsul@eecs.umich.edu write_acv 4193838Shsul@eecs.umich.edu .name(name() + ".write_acv") 4203838Shsul@eecs.umich.edu .desc("DTB write access violations") 4213838Shsul@eecs.umich.edu ; 4223838Shsul@eecs.umich.edu 4233838Shsul@eecs.umich.edu write_accesses 4243838Shsul@eecs.umich.edu .name(name() + ".write_accesses") 4253838Shsul@eecs.umich.edu .desc("DTB write accesses") 4263838Shsul@eecs.umich.edu ; 4273838Shsul@eecs.umich.edu 4283838Shsul@eecs.umich.edu hits 4293838Shsul@eecs.umich.edu .name(name() + ".hits") 4303838Shsul@eecs.umich.edu .desc("DTB hits") 4313838Shsul@eecs.umich.edu ; 4323838Shsul@eecs.umich.edu 4333838Shsul@eecs.umich.edu misses 4343838Shsul@eecs.umich.edu .name(name() + ".misses") 4353838Shsul@eecs.umich.edu .desc("DTB misses") 4363838Shsul@eecs.umich.edu ; 4373838Shsul@eecs.umich.edu 4383838Shsul@eecs.umich.edu acv 4393838Shsul@eecs.umich.edu .name(name() + ".acv") 4403838Shsul@eecs.umich.edu .desc("DTB access violations") 4413838Shsul@eecs.umich.edu ; 4423838Shsul@eecs.umich.edu 4433838Shsul@eecs.umich.edu accesses 4443838Shsul@eecs.umich.edu .name(name() + ".accesses") 4453838Shsul@eecs.umich.edu .desc("DTB accesses") 4463838Shsul@eecs.umich.edu ; 4473838Shsul@eecs.umich.edu 4483838Shsul@eecs.umich.edu hits = read_hits + write_hits; 4493838Shsul@eecs.umich.edu misses = read_misses + write_misses; 4503838Shsul@eecs.umich.edu acv = read_acv + write_acv; 4513838Shsul@eecs.umich.edu accesses = read_accesses + write_accesses; 4523838Shsul@eecs.umich.edu} 4533838Shsul@eecs.umich.edu 4543838Shsul@eecs.umich.eduFault 4553838Shsul@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const 4563838Shsul@eecs.umich.edu{ 4573838Shsul@eecs.umich.edu Addr pc = tc->readPC(); 4583838Shsul@eecs.umich.edu 4593838Shsul@eecs.umich.edu mode_type mode = 4604172Ssaidi@eecs.umich.edu (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 4613838Shsul@eecs.umich.edu 4623838Shsul@eecs.umich.edu 4633838Shsul@eecs.umich.edu /** 4643838Shsul@eecs.umich.edu * Check for alignment faults 4653838Shsul@eecs.umich.edu */ 4663838Shsul@eecs.umich.edu if (req->getVaddr() & (req->getSize() - 1)) { 4673838Shsul@eecs.umich.edu DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 4683838Shsul@eecs.umich.edu req->getSize()); 4693838Shsul@eecs.umich.edu uint64_t flags = write ? MM_STAT_WR_MASK : 0; 4703838Shsul@eecs.umich.edu return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); 4713838Shsul@eecs.umich.edu } 4723838Shsul@eecs.umich.edu 4733838Shsul@eecs.umich.edu if (PcPAL(pc)) { 4743838Shsul@eecs.umich.edu mode = (req->getFlags() & ALTMODE) ? 4753838Shsul@eecs.umich.edu (mode_type)ALT_MODE_AM( 4764172Ssaidi@eecs.umich.edu tc->readMiscRegNoEffect(IPR_ALT_MODE)) 4773838Shsul@eecs.umich.edu : mode_kernel; 4783838Shsul@eecs.umich.edu } 4793838Shsul@eecs.umich.edu 4803838Shsul@eecs.umich.edu if (req->getFlags() & PHYSICAL) { 4813838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 4823838Shsul@eecs.umich.edu } else { 4833838Shsul@eecs.umich.edu // verify that this is a good virtual address 4843838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 4853838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 4863838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 4873838Shsul@eecs.umich.edu MM_STAT_BAD_VA_MASK | 4883838Shsul@eecs.umich.edu MM_STAT_ACV_MASK; 4893838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 4903838Shsul@eecs.umich.edu } 4913838Shsul@eecs.umich.edu 4923838Shsul@eecs.umich.edu // Check for "superpage" mapping 4933838Shsul@eecs.umich.edu#if ALPHA_TLASER 4944172Ssaidi@eecs.umich.edu if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 4954088Sbinkertn@umich.edu VAddrSpaceEV5(req->getVaddr()) == 2) 4963838Shsul@eecs.umich.edu#else 4974088Sbinkertn@umich.edu if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 4983838Shsul@eecs.umich.edu#endif 4994088Sbinkertn@umich.edu { 5003838Shsul@eecs.umich.edu 5013838Shsul@eecs.umich.edu // only valid in kernel mode 5024172Ssaidi@eecs.umich.edu if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 5033838Shsul@eecs.umich.edu mode_kernel) { 5043838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 5053838Shsul@eecs.umich.edu uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 5063838Shsul@eecs.umich.edu MM_STAT_ACV_MASK); 5073838Shsul@eecs.umich.edu return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 5083838Shsul@eecs.umich.edu } 5093838Shsul@eecs.umich.edu 5103838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 5113838Shsul@eecs.umich.edu 5123838Shsul@eecs.umich.edu#if !ALPHA_TLASER 5133838Shsul@eecs.umich.edu // sign extend the physical address properly 5143838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 5153838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 5163838Shsul@eecs.umich.edu else 5173838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 5183838Shsul@eecs.umich.edu#endif 5193838Shsul@eecs.umich.edu 5203838Shsul@eecs.umich.edu } else { 5213838Shsul@eecs.umich.edu if (write) 5223838Shsul@eecs.umich.edu write_accesses++; 5233838Shsul@eecs.umich.edu else 5243838Shsul@eecs.umich.edu read_accesses++; 5253838Shsul@eecs.umich.edu 5264172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 5273838Shsul@eecs.umich.edu 5283838Shsul@eecs.umich.edu // not a physical address: need to look up pte 5293838Shsul@eecs.umich.edu PTE *pte = lookup(VAddr(req->getVaddr()).vpn(), 5303838Shsul@eecs.umich.edu asn); 5313838Shsul@eecs.umich.edu 5323838Shsul@eecs.umich.edu if (!pte) { 5333838Shsul@eecs.umich.edu // page fault 5343838Shsul@eecs.umich.edu if (write) { write_misses++; } else { read_misses++; } 5353838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 5363838Shsul@eecs.umich.edu MM_STAT_DTB_MISS_MASK; 5373838Shsul@eecs.umich.edu return (req->getFlags() & VPTE) ? 5383838Shsul@eecs.umich.edu (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), 5393838Shsul@eecs.umich.edu flags)) : 5403838Shsul@eecs.umich.edu (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), 5413838Shsul@eecs.umich.edu flags)); 5423838Shsul@eecs.umich.edu } 5433838Shsul@eecs.umich.edu 5443838Shsul@eecs.umich.edu req->setPaddr((pte->ppn << PageShift) + 5453838Shsul@eecs.umich.edu VAddr(req->getVaddr()).offset()); 5463838Shsul@eecs.umich.edu 5473838Shsul@eecs.umich.edu if (write) { 5483838Shsul@eecs.umich.edu if (!(pte->xwe & MODE2MASK(mode))) { 5493838Shsul@eecs.umich.edu // declare the instruction access fault 5503838Shsul@eecs.umich.edu write_acv++; 5513838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_WR_MASK | 5523838Shsul@eecs.umich.edu MM_STAT_ACV_MASK | 5533838Shsul@eecs.umich.edu (pte->fonw ? MM_STAT_FONW_MASK : 0); 5543838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 5553838Shsul@eecs.umich.edu } 5563838Shsul@eecs.umich.edu if (pte->fonw) { 5573838Shsul@eecs.umich.edu write_acv++; 5583838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_WR_MASK | 5593838Shsul@eecs.umich.edu MM_STAT_FONW_MASK; 5603838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 5613838Shsul@eecs.umich.edu } 5623453Sgblack@eecs.umich.edu } else { 5633838Shsul@eecs.umich.edu if (!(pte->xre & MODE2MASK(mode))) { 5643838Shsul@eecs.umich.edu read_acv++; 5653838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_ACV_MASK | 5663838Shsul@eecs.umich.edu (pte->fonr ? MM_STAT_FONR_MASK : 0); 5673838Shsul@eecs.umich.edu return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 5683453Sgblack@eecs.umich.edu } 5693838Shsul@eecs.umich.edu if (pte->fonr) { 5703838Shsul@eecs.umich.edu read_acv++; 5713838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_FONR_MASK; 5723838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 5733453Sgblack@eecs.umich.edu } 5742SN/A } 5752SN/A } 576551SN/A 5773838Shsul@eecs.umich.edu if (write) 5783838Shsul@eecs.umich.edu write_hits++; 5793838Shsul@eecs.umich.edu else 5803838Shsul@eecs.umich.edu read_hits++; 5812SN/A } 5822SN/A 5833838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 5843838Shsul@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) 5853838Shsul@eecs.umich.edu return genMachineCheckFault(); 586551SN/A 5873838Shsul@eecs.umich.edu return checkCacheability(req); 5883838Shsul@eecs.umich.edu} 5893453Sgblack@eecs.umich.edu 5903838Shsul@eecs.umich.eduPTE & 5913838Shsul@eecs.umich.eduTLB::index(bool advance) 5923838Shsul@eecs.umich.edu{ 5933838Shsul@eecs.umich.edu PTE *pte = &table[nlu]; 5943453Sgblack@eecs.umich.edu 5953838Shsul@eecs.umich.edu if (advance) 5963838Shsul@eecs.umich.edu nextnlu(); 5973453Sgblack@eecs.umich.edu 5983838Shsul@eecs.umich.edu return *pte; 5993838Shsul@eecs.umich.edu} 6003453Sgblack@eecs.umich.edu 6014088Sbinkertn@umich.edu/* end namespace AlphaISA */ } 6024088Sbinkertn@umich.edu 6033838Shsul@eecs.umich.eduDEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB) 6043453Sgblack@eecs.umich.edu 6053838Shsul@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 6063453Sgblack@eecs.umich.edu 6073838Shsul@eecs.umich.edu Param<int> size; 6083453Sgblack@eecs.umich.edu 6093838Shsul@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(ITB) 6103453Sgblack@eecs.umich.edu 6113838Shsul@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 6123453Sgblack@eecs.umich.edu 6133838Shsul@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 48) 6143453Sgblack@eecs.umich.edu 6153838Shsul@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(ITB) 6163453Sgblack@eecs.umich.edu 6173453Sgblack@eecs.umich.edu 6183838Shsul@eecs.umich.eduCREATE_SIM_OBJECT(ITB) 6193838Shsul@eecs.umich.edu{ 6203838Shsul@eecs.umich.edu return new ITB(getInstanceName(), size); 6213838Shsul@eecs.umich.edu} 6223453Sgblack@eecs.umich.edu 6233838Shsul@eecs.umich.eduREGISTER_SIM_OBJECT("AlphaITB", ITB) 6243453Sgblack@eecs.umich.edu 6253838Shsul@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 6263453Sgblack@eecs.umich.edu 6273838Shsul@eecs.umich.edu Param<int> size; 6283453Sgblack@eecs.umich.edu 6293838Shsul@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(DTB) 6303453Sgblack@eecs.umich.edu 6313838Shsul@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 6323453Sgblack@eecs.umich.edu 6333838Shsul@eecs.umich.edu INIT_PARAM_DFLT(size, "TLB size", 64) 6343453Sgblack@eecs.umich.edu 6353838Shsul@eecs.umich.eduEND_INIT_SIM_OBJECT_PARAMS(DTB) 6363453Sgblack@eecs.umich.edu 6373453Sgblack@eecs.umich.edu 6383838Shsul@eecs.umich.eduCREATE_SIM_OBJECT(DTB) 6393838Shsul@eecs.umich.edu{ 6403838Shsul@eecs.umich.edu return new DTB(getInstanceName(), size); 6413838Shsul@eecs.umich.edu} 6423453Sgblack@eecs.umich.edu 6433838Shsul@eecs.umich.eduREGISTER_SIM_OBJECT("AlphaDTB", DTB) 644