tlb.cc revision 2532 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sstream>
30#include <string>
31#include <vector>
32
33#include "arch/alpha/tlb.hh"
34#include "base/inifile.hh"
35#include "base/str.hh"
36#include "base/trace.hh"
37#include "config/alpha_tlaser.hh"
38#include "cpu/exec_context.hh"
39#include "sim/builder.hh"
40
41using namespace std;
42using namespace EV5;
43
44///////////////////////////////////////////////////////////////////////
45//
46//  Alpha TLB
47//
48#ifdef DEBUG
49bool uncacheBit39 = false;
50bool uncacheBit40 = false;
51#endif
52
53#define MODE2MASK(X)			(1 << (X))
54
55AlphaTLB::AlphaTLB(const string &name, int s)
56    : SimObject(name), size(s), nlu(0)
57{
58    table = new AlphaISA::PTE[size];
59    memset(table, 0, sizeof(AlphaISA::PTE[size]));
60}
61
62AlphaTLB::~AlphaTLB()
63{
64    if (table)
65        delete [] table;
66}
67
68// look up an entry in the TLB
69AlphaISA::PTE *
70AlphaTLB::lookup(Addr vpn, uint8_t asn) const
71{
72    // assume not found...
73    AlphaISA::PTE *retval = NULL;
74
75    PageTable::const_iterator i = lookupTable.find(vpn);
76    if (i != lookupTable.end()) {
77        while (i->first == vpn) {
78            int index = i->second;
79            AlphaISA::PTE *pte = &table[index];
80            assert(pte->valid);
81            if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
82                retval = pte;
83                break;
84            }
85
86            ++i;
87        }
88    }
89
90    DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
91            retval ? "hit" : "miss", retval ? retval->ppn : 0);
92    return retval;
93}
94
95
96Fault
97AlphaTLB::checkCacheability(RequestPtr &req)
98{
99    // in Alpha, cacheability is controlled by upper-level bits of the
100    // physical address
101
102    /*
103     * We support having the uncacheable bit in either bit 39 or bit 40.
104     * The Turbolaser platform (and EV5) support having the bit in 39, but
105     * Tsunami (which Linux assumes uses an EV6) generates accesses with
106     * the bit in 40.  So we must check for both, but we have debug flags
107     * to catch a weird case where both are used, which shouldn't happen.
108     */
109
110
111#if ALPHA_TLASER
112    if (req->getPaddr() & PAddrUncachedBit39) {
113#else
114    if (req->getPaddr() & PAddrUncachedBit43) {
115#endif
116        // IPR memory space not implemented
117        if (PAddrIprSpace(req->getPaddr())) {
118            return new UnimpFault("IPR memory space not implemented!");
119        } else {
120            // mark request as uncacheable
121            req->setFlags(req->getFlags() | UNCACHEABLE);
122
123#if !ALPHA_TLASER
124            // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
125            req->setPaddr(req->getPaddr() & PAddrUncachedMask);
126#endif
127        }
128    }
129    return NoFault;
130}
131
132
133// insert a new TLB entry
134void
135AlphaTLB::insert(Addr addr, AlphaISA::PTE &pte)
136{
137    AlphaISA::VAddr vaddr = addr;
138    if (table[nlu].valid) {
139        Addr oldvpn = table[nlu].tag;
140        PageTable::iterator i = lookupTable.find(oldvpn);
141
142        if (i == lookupTable.end())
143            panic("TLB entry not found in lookupTable");
144
145        int index;
146        while ((index = i->second) != nlu) {
147            if (table[index].tag != oldvpn)
148                panic("TLB entry not found in lookupTable");
149
150            ++i;
151        }
152
153        DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
154
155        lookupTable.erase(i);
156    }
157
158    DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
159
160    table[nlu] = pte;
161    table[nlu].tag = vaddr.vpn();
162    table[nlu].valid = true;
163
164    lookupTable.insert(make_pair(vaddr.vpn(), nlu));
165    nextnlu();
166}
167
168void
169AlphaTLB::flushAll()
170{
171    DPRINTF(TLB, "flushAll\n");
172    memset(table, 0, sizeof(AlphaISA::PTE[size]));
173    lookupTable.clear();
174    nlu = 0;
175}
176
177void
178AlphaTLB::flushProcesses()
179{
180    PageTable::iterator i = lookupTable.begin();
181    PageTable::iterator end = lookupTable.end();
182    while (i != end) {
183        int index = i->second;
184        AlphaISA::PTE *pte = &table[index];
185        assert(pte->valid);
186
187        // we can't increment i after we erase it, so save a copy and
188        // increment it to get the next entry now
189        PageTable::iterator cur = i;
190        ++i;
191
192        if (!pte->asma) {
193            DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
194            pte->valid = false;
195            lookupTable.erase(cur);
196        }
197    }
198}
199
200void
201AlphaTLB::flushAddr(Addr addr, uint8_t asn)
202{
203    AlphaISA::VAddr vaddr = addr;
204
205    PageTable::iterator i = lookupTable.find(vaddr.vpn());
206    if (i == lookupTable.end())
207        return;
208
209    while (i->first == vaddr.vpn()) {
210        int index = i->second;
211        AlphaISA::PTE *pte = &table[index];
212        assert(pte->valid);
213
214        if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) {
215            DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
216                    pte->ppn);
217
218            // invalidate this entry
219            pte->valid = false;
220
221            lookupTable.erase(i);
222        }
223
224        ++i;
225    }
226}
227
228
229void
230AlphaTLB::serialize(ostream &os)
231{
232    SERIALIZE_SCALAR(size);
233    SERIALIZE_SCALAR(nlu);
234
235    for (int i = 0; i < size; i++) {
236        nameOut(os, csprintf("%s.PTE%d", name(), i));
237        table[i].serialize(os);
238    }
239}
240
241void
242AlphaTLB::unserialize(Checkpoint *cp, const string &section)
243{
244    UNSERIALIZE_SCALAR(size);
245    UNSERIALIZE_SCALAR(nlu);
246
247    for (int i = 0; i < size; i++) {
248        table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
249        if (table[i].valid) {
250            lookupTable.insert(make_pair(table[i].tag, i));
251        }
252    }
253}
254
255
256///////////////////////////////////////////////////////////////////////
257//
258//  Alpha ITB
259//
260AlphaITB::AlphaITB(const std::string &name, int size)
261    : AlphaTLB(name, size)
262{}
263
264
265void
266AlphaITB::regStats()
267{
268    hits
269        .name(name() + ".hits")
270        .desc("ITB hits");
271    misses
272        .name(name() + ".misses")
273        .desc("ITB misses");
274    acv
275        .name(name() + ".acv")
276        .desc("ITB acv");
277    accesses
278        .name(name() + ".accesses")
279        .desc("ITB accesses");
280
281    accesses = hits + misses;
282}
283
284
285Fault
286AlphaITB::translate(RequestPtr &req, ExecContext *xc) const
287{
288    if (AlphaISA::PcPAL(req->getVaddr())) {
289        // strip off PAL PC marker (lsb is 1)
290        req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
291        hits++;
292        return NoFault;
293    }
294
295    if (req->getFlags() & PHYSICAL) {
296        req->setPaddr(req->getVaddr());
297    } else {
298        // verify that this is a good virtual address
299        if (!validVirtualAddress(req->getVaddr())) {
300            acv++;
301            return new ItbAcvFault(req->getVaddr());
302        }
303
304
305        // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
306        // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
307#if ALPHA_TLASER
308        if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
309            VAddrSpaceEV5(req->getVaddr()) == 2) {
310#else
311        if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
312#endif
313            // only valid in kernel mode
314            if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
315                AlphaISA::mode_kernel) {
316                acv++;
317                return new ItbAcvFault(req->getVaddr());
318            }
319
320            req->setPaddr(req->getVaddr() & PAddrImplMask);
321
322#if !ALPHA_TLASER
323            // sign extend the physical address properly
324            if (req->getPaddr() & PAddrUncachedBit40)
325                req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
326            else
327                req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
328#endif
329
330        } else {
331            // not a physical address: need to look up pte
332            int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
333            AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
334                                        asn);
335
336            if (!pte) {
337                misses++;
338                return new ItbPageFault(req->getVaddr());
339            }
340
341            req->setPaddr((pte->ppn << AlphaISA::PageShift) +
342                          (AlphaISA::VAddr(req->getVaddr()).offset()
343                           & ~3));
344
345            // check permissions for this access
346            if (!(pte->xre &
347                  (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
348                // instruction access fault
349                acv++;
350                return new ItbAcvFault(req->getVaddr());
351            }
352
353            hits++;
354        }
355    }
356
357    // check that the physical address is ok (catch bad physical addresses)
358    if (req->getPaddr() & ~PAddrImplMask)
359        return genMachineCheckFault();
360
361    return checkCacheability(req);
362
363}
364
365///////////////////////////////////////////////////////////////////////
366//
367//  Alpha DTB
368//
369AlphaDTB::AlphaDTB(const std::string &name, int size)
370    : AlphaTLB(name, size)
371{}
372
373void
374AlphaDTB::regStats()
375{
376    read_hits
377        .name(name() + ".read_hits")
378        .desc("DTB read hits")
379        ;
380
381    read_misses
382        .name(name() + ".read_misses")
383        .desc("DTB read misses")
384        ;
385
386    read_acv
387        .name(name() + ".read_acv")
388        .desc("DTB read access violations")
389        ;
390
391    read_accesses
392        .name(name() + ".read_accesses")
393        .desc("DTB read accesses")
394        ;
395
396    write_hits
397        .name(name() + ".write_hits")
398        .desc("DTB write hits")
399        ;
400
401    write_misses
402        .name(name() + ".write_misses")
403        .desc("DTB write misses")
404        ;
405
406    write_acv
407        .name(name() + ".write_acv")
408        .desc("DTB write access violations")
409        ;
410
411    write_accesses
412        .name(name() + ".write_accesses")
413        .desc("DTB write accesses")
414        ;
415
416    hits
417        .name(name() + ".hits")
418        .desc("DTB hits")
419        ;
420
421    misses
422        .name(name() + ".misses")
423        .desc("DTB misses")
424        ;
425
426    acv
427        .name(name() + ".acv")
428        .desc("DTB access violations")
429        ;
430
431    accesses
432        .name(name() + ".accesses")
433        .desc("DTB accesses")
434        ;
435
436    hits = read_hits + write_hits;
437    misses = read_misses + write_misses;
438    acv = read_acv + write_acv;
439    accesses = read_accesses + write_accesses;
440}
441
442Fault
443AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const
444{
445    Addr pc = xc->readPC();
446
447    AlphaISA::mode_type mode =
448        (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM));
449
450
451    /**
452     * Check for alignment faults
453     */
454    if (req->getVaddr() & (req->getSize() - 1)) {
455        DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
456                req->getSize());
457        uint64_t flags = write ? MM_STAT_WR_MASK : 0;
458        return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
459    }
460
461    if (pc & 0x1) {
462        mode = (req->getFlags() & ALTMODE) ?
463            (AlphaISA::mode_type)ALT_MODE_AM(
464                xc->readMiscReg(AlphaISA::IPR_ALT_MODE))
465            : AlphaISA::mode_kernel;
466    }
467
468    if (req->getFlags() & PHYSICAL) {
469        req->setPaddr(req->getVaddr());
470    } else {
471        // verify that this is a good virtual address
472        if (!validVirtualAddress(req->getVaddr())) {
473            if (write) { write_acv++; } else { read_acv++; }
474            uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
475                MM_STAT_BAD_VA_MASK |
476                MM_STAT_ACV_MASK;
477            return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
478        }
479
480        // Check for "superpage" mapping
481#if ALPHA_TLASER
482        if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
483            VAddrSpaceEV5(req->getVaddr()) == 2) {
484#else
485        if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
486#endif
487
488            // only valid in kernel mode
489            if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
490                AlphaISA::mode_kernel) {
491                if (write) { write_acv++; } else { read_acv++; }
492                uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
493                                  MM_STAT_ACV_MASK);
494                return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
495            }
496
497            req->setPaddr(req->getVaddr() & PAddrImplMask);
498
499#if !ALPHA_TLASER
500            // sign extend the physical address properly
501            if (req->getPaddr() & PAddrUncachedBit40)
502                req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
503            else
504                req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
505#endif
506
507        } else {
508            if (write)
509                write_accesses++;
510            else
511                read_accesses++;
512
513            int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
514
515            // not a physical address: need to look up pte
516            AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
517                                        asn);
518
519            if (!pte) {
520                // page fault
521                if (write) { write_misses++; } else { read_misses++; }
522                uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
523                    MM_STAT_DTB_MISS_MASK;
524                return (req->getFlags() & VPTE) ?
525                    (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
526                                              flags)) :
527                    (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
528                                              flags));
529            }
530
531            req->setPaddr((pte->ppn << AlphaISA::PageShift) +
532                AlphaISA::VAddr(req->getVaddr()).offset());
533
534            if (write) {
535                if (!(pte->xwe & MODE2MASK(mode))) {
536                    // declare the instruction access fault
537                    write_acv++;
538                    uint64_t flags = MM_STAT_WR_MASK |
539                        MM_STAT_ACV_MASK |
540                        (pte->fonw ? MM_STAT_FONW_MASK : 0);
541                    return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
542                }
543                if (pte->fonw) {
544                    write_acv++;
545                    uint64_t flags = MM_STAT_WR_MASK |
546                        MM_STAT_FONW_MASK;
547                    return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
548                }
549            } else {
550                if (!(pte->xre & MODE2MASK(mode))) {
551                    read_acv++;
552                    uint64_t flags = MM_STAT_ACV_MASK |
553                        (pte->fonr ? MM_STAT_FONR_MASK : 0);
554                    return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
555                }
556                if (pte->fonr) {
557                    read_acv++;
558                    uint64_t flags = MM_STAT_FONR_MASK;
559                    return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
560                }
561            }
562        }
563
564        if (write)
565            write_hits++;
566        else
567            read_hits++;
568    }
569
570    // check that the physical address is ok (catch bad physical addresses)
571    if (req->getPaddr() & ~PAddrImplMask)
572        return genMachineCheckFault();
573
574    return checkCacheability(req);
575}
576
577AlphaISA::PTE &
578AlphaTLB::index(bool advance)
579{
580    AlphaISA::PTE *pte = &table[nlu];
581
582    if (advance)
583        nextnlu();
584
585    return *pte;
586}
587
588DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB)
589
590BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
591
592    Param<int> size;
593
594END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
595
596BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB)
597
598    INIT_PARAM_DFLT(size, "TLB size", 48)
599
600END_INIT_SIM_OBJECT_PARAMS(AlphaITB)
601
602
603CREATE_SIM_OBJECT(AlphaITB)
604{
605    return new AlphaITB(getInstanceName(), size);
606}
607
608REGISTER_SIM_OBJECT("AlphaITB", AlphaITB)
609
610BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
611
612    Param<int> size;
613
614END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
615
616BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
617
618    INIT_PARAM_DFLT(size, "TLB size", 64)
619
620END_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
621
622
623CREATE_SIM_OBJECT(AlphaDTB)
624{
625    return new AlphaDTB(getInstanceName(), size);
626}
627
628REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB)
629
630