tlb.cc revision 2521
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sstream> 30#include <string> 31#include <vector> 32 33#include "arch/alpha/tlb.hh" 34#include "base/inifile.hh" 35#include "base/str.hh" 36#include "base/trace.hh" 37#include "config/alpha_tlaser.hh" 38#include "cpu/exec_context.hh" 39#include "sim/builder.hh" 40 41using namespace std; 42using namespace EV5; 43 44/////////////////////////////////////////////////////////////////////// 45// 46// Alpha TLB 47// 48#ifdef DEBUG 49bool uncacheBit39 = false; 50bool uncacheBit40 = false; 51#endif 52 53#define MODE2MASK(X) (1 << (X)) 54 55AlphaTLB::AlphaTLB(const string &name, int s) 56 : SimObject(name), size(s), nlu(0) 57{ 58 table = new AlphaISA::PTE[size]; 59 memset(table, 0, sizeof(AlphaISA::PTE[size])); 60} 61 62AlphaTLB::~AlphaTLB() 63{ 64 if (table) 65 delete [] table; 66} 67 68// look up an entry in the TLB 69AlphaISA::PTE * 70AlphaTLB::lookup(Addr vpn, uint8_t asn) const 71{ 72 // assume not found... 73 AlphaISA::PTE *retval = NULL; 74 75 PageTable::const_iterator i = lookupTable.find(vpn); 76 if (i != lookupTable.end()) { 77 while (i->first == vpn) { 78 int index = i->second; 79 AlphaISA::PTE *pte = &table[index]; 80 assert(pte->valid); 81 if (vpn == pte->tag && (pte->asma || pte->asn == asn)) { 82 retval = pte; 83 break; 84 } 85 86 ++i; 87 } 88 } 89 90 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 91 retval ? "hit" : "miss", retval ? retval->ppn : 0); 92 return retval; 93} 94 95 96Fault 97AlphaTLB::checkCacheability(CpuRequestPtr &req) 98{ 99 // in Alpha, cacheability is controlled by upper-level bits of the 100 // physical address 101 102 /* 103 * We support having the uncacheable bit in either bit 39 or bit 40. 104 * The Turbolaser platform (and EV5) support having the bit in 39, but 105 * Tsunami (which Linux assumes uses an EV6) generates accesses with 106 * the bit in 40. So we must check for both, but we have debug flags 107 * to catch a weird case where both are used, which shouldn't happen. 108 */ 109 110 111#if ALPHA_TLASER 112 if (req->paddr & PAddrUncachedBit39) { 113#else 114 if (req->paddr & PAddrUncachedBit43) { 115#endif 116 // IPR memory space not implemented 117 if (PAddrIprSpace(req->paddr)) { 118 return new UnimpFault("IPR memory space not implemented!"); 119 } else { 120 // mark request as uncacheable 121 req->flags |= UNCACHEABLE; 122 123#if !ALPHA_TLASER 124 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) 125 req->paddr &= PAddrUncachedMask; 126#endif 127 } 128 } 129 return NoFault; 130} 131 132 133// insert a new TLB entry 134void 135AlphaTLB::insert(Addr addr, AlphaISA::PTE &pte) 136{ 137 AlphaISA::VAddr vaddr = addr; 138 if (table[nlu].valid) { 139 Addr oldvpn = table[nlu].tag; 140 PageTable::iterator i = lookupTable.find(oldvpn); 141 142 if (i == lookupTable.end()) 143 panic("TLB entry not found in lookupTable"); 144 145 int index; 146 while ((index = i->second) != nlu) { 147 if (table[index].tag != oldvpn) 148 panic("TLB entry not found in lookupTable"); 149 150 ++i; 151 } 152 153 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 154 155 lookupTable.erase(i); 156 } 157 158 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn); 159 160 table[nlu] = pte; 161 table[nlu].tag = vaddr.vpn(); 162 table[nlu].valid = true; 163 164 lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 165 nextnlu(); 166} 167 168void 169AlphaTLB::flushAll() 170{ 171 DPRINTF(TLB, "flushAll\n"); 172 memset(table, 0, sizeof(AlphaISA::PTE[size])); 173 lookupTable.clear(); 174 nlu = 0; 175} 176 177void 178AlphaTLB::flushProcesses() 179{ 180 PageTable::iterator i = lookupTable.begin(); 181 PageTable::iterator end = lookupTable.end(); 182 while (i != end) { 183 int index = i->second; 184 AlphaISA::PTE *pte = &table[index]; 185 assert(pte->valid); 186 187 // we can't increment i after we erase it, so save a copy and 188 // increment it to get the next entry now 189 PageTable::iterator cur = i; 190 ++i; 191 192 if (!pte->asma) { 193 DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn); 194 pte->valid = false; 195 lookupTable.erase(cur); 196 } 197 } 198} 199 200void 201AlphaTLB::flushAddr(Addr addr, uint8_t asn) 202{ 203 AlphaISA::VAddr vaddr = addr; 204 205 PageTable::iterator i = lookupTable.find(vaddr.vpn()); 206 if (i == lookupTable.end()) 207 return; 208 209 while (i->first == vaddr.vpn()) { 210 int index = i->second; 211 AlphaISA::PTE *pte = &table[index]; 212 assert(pte->valid); 213 214 if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) { 215 DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 216 pte->ppn); 217 218 // invalidate this entry 219 pte->valid = false; 220 221 lookupTable.erase(i); 222 } 223 224 ++i; 225 } 226} 227 228 229void 230AlphaTLB::serialize(ostream &os) 231{ 232 SERIALIZE_SCALAR(size); 233 SERIALIZE_SCALAR(nlu); 234 235 for (int i = 0; i < size; i++) { 236 nameOut(os, csprintf("%s.PTE%d", name(), i)); 237 table[i].serialize(os); 238 } 239} 240 241void 242AlphaTLB::unserialize(Checkpoint *cp, const string §ion) 243{ 244 UNSERIALIZE_SCALAR(size); 245 UNSERIALIZE_SCALAR(nlu); 246 247 for (int i = 0; i < size; i++) { 248 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 249 if (table[i].valid) { 250 lookupTable.insert(make_pair(table[i].tag, i)); 251 } 252 } 253} 254 255 256/////////////////////////////////////////////////////////////////////// 257// 258// Alpha ITB 259// 260AlphaITB::AlphaITB(const std::string &name, int size) 261 : AlphaTLB(name, size) 262{} 263 264 265void 266AlphaITB::regStats() 267{ 268 hits 269 .name(name() + ".hits") 270 .desc("ITB hits"); 271 misses 272 .name(name() + ".misses") 273 .desc("ITB misses"); 274 acv 275 .name(name() + ".acv") 276 .desc("ITB acv"); 277 accesses 278 .name(name() + ".accesses") 279 .desc("ITB accesses"); 280 281 accesses = hits + misses; 282} 283 284 285Fault 286AlphaITB::translate(CpuRequestPtr &req, ExecContext *xc) const 287{ 288 if (AlphaISA::PcPAL(req->vaddr)) { 289 // strip off PAL PC marker (lsb is 1) 290 req->paddr = (req->vaddr & ~3) & PAddrImplMask; 291 hits++; 292 return NoFault; 293 } 294 295 if (req->flags & PHYSICAL) { 296 req->paddr = req->vaddr; 297 } else { 298 // verify that this is a good virtual address 299 if (!validVirtualAddress(req->vaddr)) { 300 acv++; 301 return new ItbAcvFault(req->vaddr); 302 } 303 304 305 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 306 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 307#if ALPHA_TLASER 308 if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && 309 VAddrSpaceEV5(req->vaddr) == 2) { 310#else 311 if (VAddrSpaceEV6(req->vaddr) == 0x7e) { 312#endif 313 // only valid in kernel mode 314 if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) != 315 AlphaISA::mode_kernel) { 316 acv++; 317 return new ItbAcvFault(req->vaddr); 318 } 319 320 req->paddr = req->vaddr & PAddrImplMask; 321 322#if !ALPHA_TLASER 323 // sign extend the physical address properly 324 if (req->paddr & PAddrUncachedBit40) 325 req->paddr |= ULL(0xf0000000000); 326 else 327 req->paddr &= ULL(0xffffffffff); 328#endif 329 330 } else { 331 // not a physical address: need to look up pte 332 int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN)); 333 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(), 334 asn); 335 336 if (!pte) { 337 misses++; 338 return new ItbPageFault(req->vaddr); 339 } 340 341 req->paddr = (pte->ppn << AlphaISA::PageShift) + 342 (AlphaISA::VAddr(req->vaddr).offset() & ~3); 343 344 // check permissions for this access 345 if (!(pte->xre & 346 (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) { 347 // instruction access fault 348 acv++; 349 return new ItbAcvFault(req->vaddr); 350 } 351 352 hits++; 353 } 354 } 355 356 // check that the physical address is ok (catch bad physical addresses) 357 if (req->paddr & ~PAddrImplMask) 358 return genMachineCheckFault(); 359 360 return checkCacheability(req); 361 362} 363 364/////////////////////////////////////////////////////////////////////// 365// 366// Alpha DTB 367// 368AlphaDTB::AlphaDTB(const std::string &name, int size) 369 : AlphaTLB(name, size) 370{} 371 372void 373AlphaDTB::regStats() 374{ 375 read_hits 376 .name(name() + ".read_hits") 377 .desc("DTB read hits") 378 ; 379 380 read_misses 381 .name(name() + ".read_misses") 382 .desc("DTB read misses") 383 ; 384 385 read_acv 386 .name(name() + ".read_acv") 387 .desc("DTB read access violations") 388 ; 389 390 read_accesses 391 .name(name() + ".read_accesses") 392 .desc("DTB read accesses") 393 ; 394 395 write_hits 396 .name(name() + ".write_hits") 397 .desc("DTB write hits") 398 ; 399 400 write_misses 401 .name(name() + ".write_misses") 402 .desc("DTB write misses") 403 ; 404 405 write_acv 406 .name(name() + ".write_acv") 407 .desc("DTB write access violations") 408 ; 409 410 write_accesses 411 .name(name() + ".write_accesses") 412 .desc("DTB write accesses") 413 ; 414 415 hits 416 .name(name() + ".hits") 417 .desc("DTB hits") 418 ; 419 420 misses 421 .name(name() + ".misses") 422 .desc("DTB misses") 423 ; 424 425 acv 426 .name(name() + ".acv") 427 .desc("DTB access violations") 428 ; 429 430 accesses 431 .name(name() + ".accesses") 432 .desc("DTB accesses") 433 ; 434 435 hits = read_hits + write_hits; 436 misses = read_misses + write_misses; 437 acv = read_acv + write_acv; 438 accesses = read_accesses + write_accesses; 439} 440 441Fault 442AlphaDTB::translate(CpuRequestPtr &req, ExecContext *xc, bool write) const 443{ 444 Addr pc = xc->readPC(); 445 446 AlphaISA::mode_type mode = 447 (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)); 448 449 450 /** 451 * Check for alignment faults 452 */ 453 if (req->vaddr & (req->size - 1)) { 454 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr, 455 req->size); 456 uint64_t flags = write ? MM_STAT_WR_MASK : 0; 457 return new DtbAlignmentFault(req->vaddr, req->flags, flags); 458 } 459 460 if (pc & 0x1) { 461 mode = (req->flags & ALTMODE) ? 462 (AlphaISA::mode_type)ALT_MODE_AM( 463 xc->readMiscReg(AlphaISA::IPR_ALT_MODE)) 464 : AlphaISA::mode_kernel; 465 } 466 467 if (req->flags & PHYSICAL) { 468 req->paddr = req->vaddr; 469 } else { 470 // verify that this is a good virtual address 471 if (!validVirtualAddress(req->vaddr)) { 472 if (write) { write_acv++; } else { read_acv++; } 473 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 474 MM_STAT_BAD_VA_MASK | 475 MM_STAT_ACV_MASK; 476 return new DtbPageFault(req->vaddr, req->flags, flags); 477 } 478 479 // Check for "superpage" mapping 480#if ALPHA_TLASER 481 if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && 482 VAddrSpaceEV5(req->vaddr) == 2) { 483#else 484 if (VAddrSpaceEV6(req->vaddr) == 0x7e) { 485#endif 486 487 // only valid in kernel mode 488 if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) != 489 AlphaISA::mode_kernel) { 490 if (write) { write_acv++; } else { read_acv++; } 491 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 492 MM_STAT_ACV_MASK); 493 return new DtbAcvFault(req->vaddr, req->flags, flags); 494 } 495 496 req->paddr = req->vaddr & PAddrImplMask; 497 498#if !ALPHA_TLASER 499 // sign extend the physical address properly 500 if (req->paddr & PAddrUncachedBit40) 501 req->paddr |= ULL(0xf0000000000); 502 else 503 req->paddr &= ULL(0xffffffffff); 504#endif 505 506 } else { 507 if (write) 508 write_accesses++; 509 else 510 read_accesses++; 511 512 int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN)); 513 514 // not a physical address: need to look up pte 515 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(), 516 asn); 517 518 if (!pte) { 519 // page fault 520 if (write) { write_misses++; } else { read_misses++; } 521 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 522 MM_STAT_DTB_MISS_MASK; 523 return (req->flags & VPTE) ? 524 (Fault)(new PDtbMissFault(req->vaddr, req->flags, 525 flags)) : 526 (Fault)(new NDtbMissFault(req->vaddr, req->flags, 527 flags)); 528 } 529 530 req->paddr = (pte->ppn << AlphaISA::PageShift) + 531 AlphaISA::VAddr(req->vaddr).offset(); 532 533 if (write) { 534 if (!(pte->xwe & MODE2MASK(mode))) { 535 // declare the instruction access fault 536 write_acv++; 537 uint64_t flags = MM_STAT_WR_MASK | 538 MM_STAT_ACV_MASK | 539 (pte->fonw ? MM_STAT_FONW_MASK : 0); 540 return new DtbPageFault(req->vaddr, req->flags, flags); 541 } 542 if (pte->fonw) { 543 write_acv++; 544 uint64_t flags = MM_STAT_WR_MASK | 545 MM_STAT_FONW_MASK; 546 return new DtbPageFault(req->vaddr, req->flags, flags); 547 } 548 } else { 549 if (!(pte->xre & MODE2MASK(mode))) { 550 read_acv++; 551 uint64_t flags = MM_STAT_ACV_MASK | 552 (pte->fonr ? MM_STAT_FONR_MASK : 0); 553 return new DtbAcvFault(req->vaddr, req->flags, flags); 554 } 555 if (pte->fonr) { 556 read_acv++; 557 uint64_t flags = MM_STAT_FONR_MASK; 558 return new DtbPageFault(req->vaddr, req->flags, flags); 559 } 560 } 561 } 562 563 if (write) 564 write_hits++; 565 else 566 read_hits++; 567 } 568 569 // check that the physical address is ok (catch bad physical addresses) 570 if (req->paddr & ~PAddrImplMask) 571 return genMachineCheckFault(); 572 573 return checkCacheability(req); 574} 575 576AlphaISA::PTE & 577AlphaTLB::index(bool advance) 578{ 579 AlphaISA::PTE *pte = &table[nlu]; 580 581 if (advance) 582 nextnlu(); 583 584 return *pte; 585} 586 587DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB) 588 589BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) 590 591 Param<int> size; 592 593END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) 594 595BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB) 596 597 INIT_PARAM_DFLT(size, "TLB size", 48) 598 599END_INIT_SIM_OBJECT_PARAMS(AlphaITB) 600 601 602CREATE_SIM_OBJECT(AlphaITB) 603{ 604 return new AlphaITB(getInstanceName(), size); 605} 606 607REGISTER_SIM_OBJECT("AlphaITB", AlphaITB) 608 609BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) 610 611 Param<int> size; 612 613END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) 614 615BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB) 616 617 INIT_PARAM_DFLT(size, "TLB size", 64) 618 619END_INIT_SIM_OBJECT_PARAMS(AlphaDTB) 620 621 622CREATE_SIM_OBJECT(AlphaDTB) 623{ 624 return new AlphaDTB(getInstanceName(), size); 625} 626 627REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB) 628 629