tlb.cc revision 2289 
111731Sjason@lowepower.com/*
212137Sar4jc@virginia.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan
312137Sar4jc@virginia.edu * All rights reserved.
412137Sar4jc@virginia.edu *
512137Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sstream>
30#include <string>
31#include <vector>
32
33#include "arch/alpha/tlb.hh"
34#include "base/inifile.hh"
35#include "base/str.hh"
36#include "base/trace.hh"
37#include "config/alpha_tlaser.hh"
38#include "cpu/exec_context.hh"
39#include "sim/builder.hh"
40
41using namespace std;
42using namespace EV5;
43
44///////////////////////////////////////////////////////////////////////
45//
46//  Alpha TLB
47//
48#ifdef DEBUG
49bool uncacheBit39 = false;
50bool uncacheBit40 = false;
51#endif
52
53#define MODE2MASK(X)			(1 << (X))
54
55AlphaTLB::AlphaTLB(const string &name, int s)
56    : SimObject(name), size(s), nlu(0)
57{
58    table = new AlphaISA::PTE[size];
59    memset(table, 0, sizeof(AlphaISA::PTE[size]));
60}
61
62AlphaTLB::~AlphaTLB()
63{
64    if (table)
65        delete [] table;
66}
67
68// look up an entry in the TLB
69AlphaISA::PTE *
70AlphaTLB::lookup(Addr vpn, uint8_t asn) const
71{
72    // assume not found...
73    AlphaISA::PTE *retval = NULL;
74
75    PageTable::const_iterator i = lookupTable.find(vpn);
76    if (i != lookupTable.end()) {
77        while (i->first == vpn) {
78            int index = i->second;
79            AlphaISA::PTE *pte = &table[index];
80            assert(pte->valid);
81            if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
82                retval = pte;
83                break;
84            }
85
86            ++i;
87        }
88    }
89
90    DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
91            retval ? "hit" : "miss", retval ? retval->ppn : 0);
92    return retval;
93}
94
95
96void
97AlphaTLB::checkCacheability(MemReqPtr &req)
98{
99    // in Alpha, cacheability is controlled by upper-level bits of the
100    // physical address
101
102    /*
103     * We support having the uncacheable bit in either bit 39 or bit 40.
104     * The Turbolaser platform (and EV5) support having the bit in 39, but
105     * Tsunami (which Linux assumes uses an EV6) generates accesses with
106     * the bit in 40.  So we must check for both, but we have debug flags
107     * to catch a weird case where both are used, which shouldn't happen.
108     */
109
110
111#if ALPHA_TLASER
112    if (req->paddr & PAddrUncachedBit39) {
113#else
114    if (req->paddr & PAddrUncachedBit43) {
115#endif
116        // IPR memory space not implemented
117        if (PAddrIprSpace(req->paddr)) {
118            if (!req->xc->misspeculating()) {
119                switch (req->paddr) {
120                  case ULL(0xFFFFF00188):
121                    req->data = 0;
122                    break;
123
124                  default:
125                    panic("IPR memory space not implemented! PA=%x\n",
126                          req->paddr);
127                }
128            }
129        } else {
130            // mark request as uncacheable
131            req->flags |= UNCACHEABLE;
132
133#if !ALPHA_TLASER
134            // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
135            req->paddr &= PAddrUncachedMask;
136#endif
137        }
138    }
139}
140
141
142// insert a new TLB entry
143void
144AlphaTLB::insert(Addr addr, AlphaISA::PTE &pte)
145{
146    AlphaISA::VAddr vaddr = addr;
147    if (table[nlu].valid) {
148        Addr oldvpn = table[nlu].tag;
149        PageTable::iterator i = lookupTable.find(oldvpn);
150
151        if (i == lookupTable.end())
152            panic("TLB entry not found in lookupTable");
153
154        int index;
155        while ((index = i->second) != nlu) {
156            if (table[index].tag != oldvpn)
157                panic("TLB entry not found in lookupTable");
158
159            ++i;
160        }
161
162        DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
163
164        lookupTable.erase(i);
165    }
166
167    DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
168
169    table[nlu] = pte;
170    table[nlu].tag = vaddr.vpn();
171    table[nlu].valid = true;
172
173    lookupTable.insert(make_pair(vaddr.vpn(), nlu));
174    nextnlu();
175}
176
177void
178AlphaTLB::flushAll()
179{
180    DPRINTF(TLB, "flushAll\n");
181    memset(table, 0, sizeof(AlphaISA::PTE[size]));
182    lookupTable.clear();
183    nlu = 0;
184}
185
186void
187AlphaTLB::flushProcesses()
188{
189    PageTable::iterator i = lookupTable.begin();
190    PageTable::iterator end = lookupTable.end();
191    while (i != end) {
192        int index = i->second;
193        AlphaISA::PTE *pte = &table[index];
194        assert(pte->valid);
195
196        // we can't increment i after we erase it, so save a copy and
197        // increment it to get the next entry now
198        PageTable::iterator cur = i;
199        ++i;
200
201        if (!pte->asma) {
202            DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
203            pte->valid = false;
204            lookupTable.erase(cur);
205        }
206    }
207}
208
209void
210AlphaTLB::flushAddr(Addr addr, uint8_t asn)
211{
212    AlphaISA::VAddr vaddr = addr;
213
214    PageTable::iterator i = lookupTable.find(vaddr.vpn());
215    if (i == lookupTable.end())
216        return;
217
218    while (i->first == vaddr.vpn()) {
219        int index = i->second;
220        AlphaISA::PTE *pte = &table[index];
221        assert(pte->valid);
222
223        if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) {
224            DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
225                    pte->ppn);
226
227            // invalidate this entry
228            pte->valid = false;
229
230            lookupTable.erase(i);
231        }
232
233        ++i;
234    }
235}
236
237
238void
239AlphaTLB::serialize(ostream &os)
240{
241    SERIALIZE_SCALAR(size);
242    SERIALIZE_SCALAR(nlu);
243
244    for (int i = 0; i < size; i++) {
245        nameOut(os, csprintf("%s.PTE%d", name(), i));
246        table[i].serialize(os);
247    }
248}
249
250void
251AlphaTLB::unserialize(Checkpoint *cp, const string &section)
252{
253    UNSERIALIZE_SCALAR(size);
254    UNSERIALIZE_SCALAR(nlu);
255
256    for (int i = 0; i < size; i++) {
257        table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
258        if (table[i].valid) {
259            lookupTable.insert(make_pair(table[i].tag, i));
260        }
261    }
262}
263
264
265///////////////////////////////////////////////////////////////////////
266//
267//  Alpha ITB
268//
269AlphaITB::AlphaITB(const std::string &name, int size)
270    : AlphaTLB(name, size)
271{}
272
273
274void
275AlphaITB::regStats()
276{
277    hits
278        .name(name() + ".hits")
279        .desc("ITB hits");
280    misses
281        .name(name() + ".misses")
282        .desc("ITB misses");
283    acv
284        .name(name() + ".acv")
285        .desc("ITB acv");
286    accesses
287        .name(name() + ".accesses")
288        .desc("ITB accesses");
289
290    accesses = hits + misses;
291}
292
293
294Fault
295AlphaITB::translate(MemReqPtr &req) const
296{
297    ExecContext *xc = req->xc;
298
299    if (AlphaISA::PcPAL(req->vaddr)) {
300        // strip off PAL PC marker (lsb is 1)
301        req->paddr = (req->vaddr & ~3) & PAddrImplMask;
302        hits++;
303        return NoFault;
304    }
305
306    if (req->flags & PHYSICAL) {
307        req->paddr = req->vaddr;
308    } else {
309        // verify that this is a good virtual address
310        if (!validVirtualAddress(req->vaddr)) {
311            acv++;
312            return new ItbAcvFault(req->vaddr);
313        }
314
315
316        // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
317        // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
318#if ALPHA_TLASER
319        if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
320            VAddrSpaceEV5(req->vaddr) == 2) {
321#else
322        if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
323#endif
324            // only valid in kernel mode
325            if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
326                AlphaISA::mode_kernel) {
327                acv++;
328                return new ItbAcvFault(req->vaddr);
329            }
330
331            req->paddr = req->vaddr & PAddrImplMask;
332
333#if !ALPHA_TLASER
334            // sign extend the physical address properly
335            if (req->paddr & PAddrUncachedBit40)
336                req->paddr |= ULL(0xf0000000000);
337            else
338                req->paddr &= ULL(0xffffffffff);
339#endif
340
341        } else {
342            // not a physical address: need to look up pte
343            int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
344            AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
345                                        asn);
346
347            if (!pte) {
348                misses++;
349                return new ItbPageFault(req->vaddr);
350            }
351
352            req->paddr = (pte->ppn << AlphaISA::PageShift) +
353                (AlphaISA::VAddr(req->vaddr).offset() & ~3);
354
355            // check permissions for this access
356            if (!(pte->xre &
357                  (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
358                // instruction access fault
359                acv++;
360                return new ItbAcvFault(req->vaddr);
361            }
362
363            hits++;
364        }
365    }
366
367    // check that the physical address is ok (catch bad physical addresses)
368    if (req->paddr & ~PAddrImplMask)
369        return genMachineCheckFault();
370
371    checkCacheability(req);
372
373    return NoFault;
374}
375
376///////////////////////////////////////////////////////////////////////
377//
378//  Alpha DTB
379//
380AlphaDTB::AlphaDTB(const std::string &name, int size)
381    : AlphaTLB(name, size)
382{}
383
384void
385AlphaDTB::regStats()
386{
387    read_hits
388        .name(name() + ".read_hits")
389        .desc("DTB read hits")
390        ;
391
392    read_misses
393        .name(name() + ".read_misses")
394        .desc("DTB read misses")
395        ;
396
397    read_acv
398        .name(name() + ".read_acv")
399        .desc("DTB read access violations")
400        ;
401
402    read_accesses
403        .name(name() + ".read_accesses")
404        .desc("DTB read accesses")
405        ;
406
407    write_hits
408        .name(name() + ".write_hits")
409        .desc("DTB write hits")
410        ;
411
412    write_misses
413        .name(name() + ".write_misses")
414        .desc("DTB write misses")
415        ;
416
417    write_acv
418        .name(name() + ".write_acv")
419        .desc("DTB write access violations")
420        ;
421
422    write_accesses
423        .name(name() + ".write_accesses")
424        .desc("DTB write accesses")
425        ;
426
427    hits
428        .name(name() + ".hits")
429        .desc("DTB hits")
430        ;
431
432    misses
433        .name(name() + ".misses")
434        .desc("DTB misses")
435        ;
436
437    acv
438        .name(name() + ".acv")
439        .desc("DTB access violations")
440        ;
441
442    accesses
443        .name(name() + ".accesses")
444        .desc("DTB accesses")
445        ;
446
447    hits = read_hits + write_hits;
448    misses = read_misses + write_misses;
449    acv = read_acv + write_acv;
450    accesses = read_accesses + write_accesses;
451}
452
453Fault
454AlphaDTB::translate(MemReqPtr &req, bool write) const
455{
456    ExecContext *xc = req->xc;
457    Addr pc = xc->readPC();
458
459    AlphaISA::mode_type mode =
460        (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM));
461
462
463    /**
464     * Check for alignment faults
465     */
466    if (req->vaddr & (req->size - 1)) {
467        DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
468                req->size);
469        uint64_t flags = write ? MM_STAT_WR_MASK : 0;
470        return new DtbAlignmentFault(req->vaddr, req->flags, flags);
471    }
472
473    if (pc & 0x1) {
474        mode = (req->flags & ALTMODE) ?
475            (AlphaISA::mode_type)ALT_MODE_AM(
476                xc->readMiscReg(AlphaISA::IPR_ALT_MODE))
477            : AlphaISA::mode_kernel;
478    }
479
480    if (req->flags & PHYSICAL) {
481        req->paddr = req->vaddr;
482    } else {
483        // verify that this is a good virtual address
484        if (!validVirtualAddress(req->vaddr)) {
485            if (write) { write_acv++; } else { read_acv++; }
486            uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
487                MM_STAT_BAD_VA_MASK |
488                MM_STAT_ACV_MASK;
489            return new DtbPageFault(req->vaddr, req->flags, flags);
490        }
491
492        // Check for "superpage" mapping
493#if ALPHA_TLASER
494        if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
495            VAddrSpaceEV5(req->vaddr) == 2) {
496#else
497        if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
498#endif
499
500            // only valid in kernel mode
501            if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
502                AlphaISA::mode_kernel) {
503                if (write) { write_acv++; } else { read_acv++; }
504                uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
505                                  MM_STAT_ACV_MASK);
506                return new DtbAcvFault(req->vaddr, req->flags, flags);
507            }
508
509            req->paddr = req->vaddr & PAddrImplMask;
510
511#if !ALPHA_TLASER
512            // sign extend the physical address properly
513            if (req->paddr & PAddrUncachedBit40)
514                req->paddr |= ULL(0xf0000000000);
515            else
516                req->paddr &= ULL(0xffffffffff);
517#endif
518
519        } else {
520            if (write)
521                write_accesses++;
522            else
523                read_accesses++;
524
525            int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
526
527            // not a physical address: need to look up pte
528            AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
529                                        asn);
530
531            if (!pte) {
532                // page fault
533                if (write) { write_misses++; } else { read_misses++; }
534                uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
535                    MM_STAT_DTB_MISS_MASK;
536                return (req->flags & VPTE) ?
537                    (Fault)(new PDtbMissFault(req->vaddr, req->flags,
538                                              flags)) :
539                    (Fault)(new NDtbMissFault(req->vaddr, req->flags,
540                                              flags));
541            }
542
543            req->paddr = (pte->ppn << AlphaISA::PageShift) +
544                AlphaISA::VAddr(req->vaddr).offset();
545
546            if (write) {
547                if (!(pte->xwe & MODE2MASK(mode))) {
548                    // declare the instruction access fault
549                    write_acv++;
550                    uint64_t flags = MM_STAT_WR_MASK |
551                        MM_STAT_ACV_MASK |
552                        (pte->fonw ? MM_STAT_FONW_MASK : 0);
553                    return new DtbPageFault(req->vaddr, req->flags, flags);
554                }
555                if (pte->fonw) {
556                    write_acv++;
557                    uint64_t flags = MM_STAT_WR_MASK |
558                        MM_STAT_FONW_MASK;
559                    return new DtbPageFault(req->vaddr, req->flags, flags);
560                }
561            } else {
562                if (!(pte->xre & MODE2MASK(mode))) {
563                    read_acv++;
564                    uint64_t flags = MM_STAT_ACV_MASK |
565                        (pte->fonr ? MM_STAT_FONR_MASK : 0);
566                    return new DtbAcvFault(req->vaddr, req->flags, flags);
567                }
568                if (pte->fonr) {
569                    read_acv++;
570                    uint64_t flags = MM_STAT_FONR_MASK;
571                    return new DtbPageFault(req->vaddr, req->flags, flags);
572                }
573            }
574        }
575
576        if (write)
577            write_hits++;
578        else
579            read_hits++;
580    }
581
582    // check that the physical address is ok (catch bad physical addresses)
583    if (req->paddr & ~PAddrImplMask)
584        return genMachineCheckFault();
585
586    checkCacheability(req);
587
588    return NoFault;
589}
590
591AlphaISA::PTE &
592AlphaTLB::index(bool advance)
593{
594    AlphaISA::PTE *pte = &table[nlu];
595
596    if (advance)
597        nextnlu();
598
599    return *pte;
600}
601
602DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB)
603
604BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
605
606    Param<int> size;
607
608END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
609
610BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB)
611
612    INIT_PARAM_DFLT(size, "TLB size", 48)
613
614END_INIT_SIM_OBJECT_PARAMS(AlphaITB)
615
616
617CREATE_SIM_OBJECT(AlphaITB)
618{
619    return new AlphaITB(getInstanceName(), size);
620}
621
622REGISTER_SIM_OBJECT("AlphaITB", AlphaITB)
623
624BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
625
626    Param<int> size;
627
628END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
629
630BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
631
632    INIT_PARAM_DFLT(size, "TLB size", 64)
633
634END_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
635
636
637CREATE_SIM_OBJECT(AlphaDTB)
638{
639    return new AlphaDTB(getInstanceName(), size);
640}
641
642REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB)
643
644