tlb.cc revision 1865
16184SN/A/* 28842Smrinmoy.ghosh@arm.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 38842Smrinmoy.ghosh@arm.com * All rights reserved. 48842Smrinmoy.ghosh@arm.com * 58842Smrinmoy.ghosh@arm.com * Redistribution and use in source and binary forms, with or without 68842Smrinmoy.ghosh@arm.com * modification, are permitted provided that the following conditions are 78842Smrinmoy.ghosh@arm.com * met: redistributions of source code must retain the above copyright 88842Smrinmoy.ghosh@arm.com * notice, this list of conditions and the following disclaimer; 98842Smrinmoy.ghosh@arm.com * redistributions in binary form must reproduce the above copyright 108842Smrinmoy.ghosh@arm.com * notice, this list of conditions and the following disclaimer in the 118842Smrinmoy.ghosh@arm.com * documentation and/or other materials provided with the distribution; 128842Smrinmoy.ghosh@arm.com * neither the name of the copyright holders nor the names of its 138842Smrinmoy.ghosh@arm.com * contributors may be used to endorse or promote products derived from 146184SN/A * this software without specific prior written permission. 156184SN/A * 166184SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176184SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186184SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196184SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206184SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216184SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226184SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236184SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246184SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256184SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266184SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276184SN/A */ 286184SN/A 296184SN/A#include <sstream> 306184SN/A#include <string> 316184SN/A#include <vector> 326184SN/A 336184SN/A#include "arch/alpha/alpha_memory.hh" 346184SN/A#include "base/inifile.hh" 356184SN/A#include "base/str.hh" 366184SN/A#include "base/trace.hh" 376184SN/A#include "config/alpha_tlaser.hh" 386184SN/A#include "cpu/exec_context.hh" 396184SN/A#include "sim/builder.hh" 406184SN/A 416184SN/Ausing namespace std; 426184SN/Ausing namespace EV5; 436184SN/A 446226Snate@binkert.org/////////////////////////////////////////////////////////////////////// 456184SN/A// 466184SN/A// Alpha TLB 476184SN/A// 486184SN/A#ifdef DEBUG 496184SN/Abool uncacheBit39 = false; 506184SN/Abool uncacheBit40 = false; 518463SMrinmoy.Ghosh@arm.com#endif 526184SN/A 536184SN/A#define MODE2MASK(X) (1 << (X)) 546184SN/A 556184SN/AAlphaTLB::AlphaTLB(const string &name, int s) 566184SN/A : SimObject(name), size(s), nlu(0) 576184SN/A{ 586184SN/A table = new AlphaISA::PTE[size]; 596184SN/A memset(table, 0, sizeof(AlphaISA::PTE[size])); 606184SN/A} 616184SN/A 626184SN/AAlphaTLB::~AlphaTLB() 636184SN/A{ 646184SN/A if (table) 656184SN/A delete [] table; 666184SN/A} 676184SN/A 686184SN/A// look up an entry in the TLB 696184SN/AAlphaISA::PTE * 706184SN/AAlphaTLB::lookup(Addr vpn, uint8_t asn) const 716184SN/A{ 726184SN/A // assume not found... 736184SN/A AlphaISA::PTE *retval = NULL; 746184SN/A 756184SN/A PageTable::const_iterator i = lookupTable.find(vpn); 766184SN/A if (i != lookupTable.end()) { 776184SN/A while (i->first == vpn) { 786184SN/A int index = i->second; 796184SN/A AlphaISA::PTE *pte = &table[index]; 806184SN/A assert(pte->valid); 816184SN/A if (vpn == pte->tag && (pte->asma || pte->asn == asn)) { 826184SN/A retval = pte; 836184SN/A break; 846184SN/A } 856184SN/A 866184SN/A ++i; 876184SN/A } 886184SN/A } 896184SN/A 906184SN/A DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 916184SN/A retval ? "hit" : "miss", retval ? retval->ppn : 0); 926184SN/A return retval; 936184SN/A} 946184SN/A 956184SN/A 966184SN/Avoid 976184SN/AAlphaTLB::checkCacheability(MemReqPtr &req) 986184SN/A{ 996184SN/A // in Alpha, cacheability is controlled by upper-level bits of the 1006184SN/A // physical address 1016184SN/A 1026184SN/A /* 1036184SN/A * We support having the uncacheable bit in either bit 39 or bit 40. 1046184SN/A * The Turbolaser platform (and EV5) support having the bit in 39, but 1056184SN/A * Tsunami (which Linux assumes uses an EV6) generates accesses with 1066184SN/A * the bit in 40. So we must check for both, but we have debug flags 1076184SN/A * to catch a weird case where both are used, which shouldn't happen. 1086184SN/A */ 1096184SN/A 1106184SN/A 1116184SN/A#if ALPHA_TLASER 1126184SN/A if (req->paddr & PAddrUncachedBit39) { 1136184SN/A#else 1146184SN/A if (req->paddr & PAddrUncachedBit43) { 1156184SN/A#endif 1166184SN/A // IPR memory space not implemented 1176184SN/A if (PAddrIprSpace(req->paddr)) { 1186184SN/A if (!req->xc->misspeculating()) { 1196184SN/A switch (req->paddr) { 1206184SN/A case ULL(0xFFFFF00188): 1216184SN/A req->data = 0; 1226184SN/A break; 1236184SN/A 1246184SN/A default: 1256184SN/A panic("IPR memory space not implemented! PA=%x\n", 1266184SN/A req->paddr); 1276184SN/A } 1286184SN/A } 1296184SN/A } else { 1306184SN/A // mark request as uncacheable 1316184SN/A req->flags |= UNCACHEABLE; 1326184SN/A 1336184SN/A#if !ALPHA_TLASER 1346184SN/A // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) 1356184SN/A req->paddr &= PAddrUncachedMask; 1366184SN/A#endif 1376184SN/A } 1386184SN/A } 1396184SN/A} 1406184SN/A 1416184SN/A 1426184SN/A// insert a new TLB entry 1436184SN/Avoid 1446184SN/AAlphaTLB::insert(Addr addr, AlphaISA::PTE &pte) 1456184SN/A{ 1466184SN/A AlphaISA::VAddr vaddr = addr; 1476184SN/A if (table[nlu].valid) { 1486184SN/A Addr oldvpn = table[nlu].tag; 1496184SN/A PageTable::iterator i = lookupTable.find(oldvpn); 1506184SN/A 1516184SN/A if (i == lookupTable.end()) 1526184SN/A panic("TLB entry not found in lookupTable"); 1536184SN/A 1546184SN/A int index; 1556184SN/A while ((index = i->second) != nlu) { 1566184SN/A if (table[index].tag != oldvpn) 1576184SN/A panic("TLB entry not found in lookupTable"); 1586184SN/A 1596184SN/A ++i; 1606184SN/A } 1618842Smrinmoy.ghosh@arm.com 1628842Smrinmoy.ghosh@arm.com DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 1638842Smrinmoy.ghosh@arm.com 1648842Smrinmoy.ghosh@arm.com lookupTable.erase(i); 1658842Smrinmoy.ghosh@arm.com } 1668842Smrinmoy.ghosh@arm.com 1678842Smrinmoy.ghosh@arm.com DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn); 1688842Smrinmoy.ghosh@arm.com 1698842Smrinmoy.ghosh@arm.com table[nlu] = pte; 1708842Smrinmoy.ghosh@arm.com table[nlu].tag = vaddr.vpn(); 1718842Smrinmoy.ghosh@arm.com table[nlu].valid = true; 1728842Smrinmoy.ghosh@arm.com 1736184SN/A lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 1746184SN/A nextnlu(); 1756184SN/A} 1766184SN/A 1776184SN/Avoid 1786184SN/AAlphaTLB::flushAll() 1796184SN/A{ 1806184SN/A DPRINTF(TLB, "flushAll\n"); 1816184SN/A memset(table, 0, sizeof(AlphaISA::PTE[size])); 1826184SN/A lookupTable.clear(); 1836184SN/A nlu = 0; 1846184SN/A} 1856184SN/A 1866184SN/Avoid 1876184SN/AAlphaTLB::flushProcesses() 1886184SN/A{ 1896184SN/A PageTable::iterator i = lookupTable.begin(); 1906184SN/A PageTable::iterator end = lookupTable.end(); 1916184SN/A while (i != end) { 1926184SN/A int index = i->second; 1936184SN/A AlphaISA::PTE *pte = &table[index]; 1946184SN/A assert(pte->valid); 1956184SN/A 1966184SN/A // we can't increment i after we erase it, so save a copy and 1976184SN/A // increment it to get the next entry now 1986184SN/A PageTable::iterator cur = i; 1996184SN/A ++i; 2006184SN/A 2018842Smrinmoy.ghosh@arm.com if (!pte->asma) { 2026184SN/A DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn); 2036184SN/A pte->valid = false; 2046184SN/A lookupTable.erase(cur); 2056184SN/A } 2066184SN/A } 2076184SN/A} 2086184SN/A 2096184SN/Avoid 2106184SN/AAlphaTLB::flushAddr(Addr addr, uint8_t asn) 2116184SN/A{ 2126184SN/A AlphaISA::VAddr vaddr = addr; 2138842Smrinmoy.ghosh@arm.com 2146184SN/A PageTable::iterator i = lookupTable.find(vaddr.vpn()); 2156184SN/A if (i == lookupTable.end()) 2166184SN/A return; 2178842Smrinmoy.ghosh@arm.com 2186184SN/A while (i->first == vaddr.vpn()) { 2196184SN/A int index = i->second; 2206184SN/A AlphaISA::PTE *pte = &table[index]; 2216184SN/A assert(pte->valid); 2226184SN/A 2238842Smrinmoy.ghosh@arm.com if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) { 2246184SN/A DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 2256184SN/A pte->ppn); 2266184SN/A 2278842Smrinmoy.ghosh@arm.com // invalidate this entry 2286184SN/A pte->valid = false; 2296184SN/A 2306184SN/A lookupTable.erase(i); 2316184SN/A } 2326184SN/A 2336184SN/A ++i; 2346184SN/A } 2356184SN/A} 2366184SN/A 2376184SN/A 2386184SN/Avoid 2396184SN/AAlphaTLB::serialize(ostream &os) 2406184SN/A{ 2418487SAli.Saidi@ARM.com SERIALIZE_SCALAR(size); 2428842Smrinmoy.ghosh@arm.com SERIALIZE_SCALAR(nlu); 2436184SN/A 2446184SN/A for (int i = 0; i < size; i++) { 2456184SN/A nameOut(os, csprintf("%s.PTE%d", name(), i)); 2466184SN/A table[i].serialize(os); 2476184SN/A } 2486184SN/A} 2498842Smrinmoy.ghosh@arm.com 2508842Smrinmoy.ghosh@arm.comvoid 2516184SN/AAlphaTLB::unserialize(Checkpoint *cp, const string §ion) 2526184SN/A{ 2538842Smrinmoy.ghosh@arm.com UNSERIALIZE_SCALAR(size); 2546184SN/A UNSERIALIZE_SCALAR(nlu); 2556184SN/A 2566184SN/A for (int i = 0; i < size; i++) { 2576184SN/A table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 2586184SN/A if (table[i].valid) { 2596184SN/A lookupTable.insert(make_pair(table[i].tag, i)); 2606184SN/A } 2616184SN/A } 2626184SN/A} 2638843Smrinmoy.ghosh@arm.com 2648843Smrinmoy.ghosh@arm.com 2658843Smrinmoy.ghosh@arm.com/////////////////////////////////////////////////////////////////////// 2668843Smrinmoy.ghosh@arm.com// 2678843Smrinmoy.ghosh@arm.com// Alpha ITB 2688843Smrinmoy.ghosh@arm.com// 2698843Smrinmoy.ghosh@arm.comAlphaITB::AlphaITB(const std::string &name, int size) 2708843Smrinmoy.ghosh@arm.com : AlphaTLB(name, size) 2718843Smrinmoy.ghosh@arm.com{} 2728843Smrinmoy.ghosh@arm.com 2738843Smrinmoy.ghosh@arm.com 2748843Smrinmoy.ghosh@arm.comvoid 2758843Smrinmoy.ghosh@arm.comAlphaITB::regStats() 2768843Smrinmoy.ghosh@arm.com{ 2778843Smrinmoy.ghosh@arm.com hits 2788843Smrinmoy.ghosh@arm.com .name(name() + ".hits") 2798843Smrinmoy.ghosh@arm.com .desc("ITB hits"); 2808843Smrinmoy.ghosh@arm.com misses 2818843Smrinmoy.ghosh@arm.com .name(name() + ".misses") 2828843Smrinmoy.ghosh@arm.com .desc("ITB misses"); 2838843Smrinmoy.ghosh@arm.com acv 2848843Smrinmoy.ghosh@arm.com .name(name() + ".acv") 2858463SMrinmoy.Ghosh@arm.com .desc("ITB acv"); 2868843Smrinmoy.ghosh@arm.com accesses 2878843Smrinmoy.ghosh@arm.com .name(name() + ".accesses") 2888843Smrinmoy.ghosh@arm.com .desc("ITB accesses"); 2898843Smrinmoy.ghosh@arm.com 2908843Smrinmoy.ghosh@arm.com accesses = hits + misses; 2918843Smrinmoy.ghosh@arm.com} 2928843Smrinmoy.ghosh@arm.com 2938843Smrinmoy.ghosh@arm.comvoid 2948843Smrinmoy.ghosh@arm.comAlphaITB::fault(Addr pc, ExecContext *xc) const 2958843Smrinmoy.ghosh@arm.com{ 2968843Smrinmoy.ghosh@arm.com uint64_t *ipr = xc->regs.ipr; 2978843Smrinmoy.ghosh@arm.com 2988843Smrinmoy.ghosh@arm.com if (!xc->misspeculating()) { 2998843Smrinmoy.ghosh@arm.com ipr[AlphaISA::IPR_ITB_TAG] = pc; 3008843Smrinmoy.ghosh@arm.com ipr[AlphaISA::IPR_IFAULT_VA_FORM] = 3018843Smrinmoy.ghosh@arm.com ipr[AlphaISA::IPR_IVPTBR] | (AlphaISA::VAddr(pc).vpn() << 3); 3028843Smrinmoy.ghosh@arm.com } 3036184SN/A} 3048843Smrinmoy.ghosh@arm.com 3058843Smrinmoy.ghosh@arm.com 3068843Smrinmoy.ghosh@arm.comFault 3078843Smrinmoy.ghosh@arm.comAlphaITB::translate(MemReqPtr &req) const 3088843Smrinmoy.ghosh@arm.com{ 3098843Smrinmoy.ghosh@arm.com InternalProcReg *ipr = req->xc->regs.ipr; 3108842Smrinmoy.ghosh@arm.com 3118843Smrinmoy.ghosh@arm.com if (AlphaISA::PcPAL(req->vaddr)) { 3128843Smrinmoy.ghosh@arm.com // strip off PAL PC marker (lsb is 1) 3138843Smrinmoy.ghosh@arm.com req->paddr = (req->vaddr & ~3) & PAddrImplMask; 3148843Smrinmoy.ghosh@arm.com hits++; 3158843Smrinmoy.ghosh@arm.com return No_Fault; 3168843Smrinmoy.ghosh@arm.com } 3178842Smrinmoy.ghosh@arm.com 3188843Smrinmoy.ghosh@arm.com if (req->flags & PHYSICAL) { 3198843Smrinmoy.ghosh@arm.com req->paddr = req->vaddr; 3208463SMrinmoy.Ghosh@arm.com } else { 3218463SMrinmoy.Ghosh@arm.com // verify that this is a good virtual address 3226184SN/A if (!validVirtualAddress(req->vaddr)) { 3236184SN/A fault(req->vaddr, req->xc); 3248843Smrinmoy.ghosh@arm.com acv++; 3256184SN/A return ITB_Acv_Fault; 3266184SN/A } 3276184SN/A 3286184SN/A 3296184SN/A // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 3306184SN/A // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 3316184SN/A#if ALPHA_TLASER 3326184SN/A if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && 3336184SN/A VAddrSpaceEV5(req->vaddr) == 2) { 3346184SN/A#else 3356184SN/A if (VAddrSpaceEV6(req->vaddr) == 0x7e) { 3366184SN/A#endif 3376184SN/A // only valid in kernel mode 3386184SN/A if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != 3396184SN/A AlphaISA::mode_kernel) { 3406184SN/A fault(req->vaddr, req->xc); 3416184SN/A acv++; 3426184SN/A return ITB_Acv_Fault; 3436184SN/A } 3446184SN/A 3456184SN/A req->paddr = req->vaddr & PAddrImplMask; 3466184SN/A 3476184SN/A#if !ALPHA_TLASER 3486184SN/A // sign extend the physical address properly 3496184SN/A if (req->paddr & PAddrUncachedBit40) 350 req->paddr |= ULL(0xf0000000000); 351 else 352 req->paddr &= ULL(0xffffffffff); 353#endif 354 355 } else { 356 // not a physical address: need to look up pte 357 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(), 358 DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); 359 360 if (!pte) { 361 fault(req->vaddr, req->xc); 362 misses++; 363 return ITB_Fault_Fault; 364 } 365 366 req->paddr = (pte->ppn << AlphaISA::PageShift) + 367 (AlphaISA::VAddr(req->vaddr).offset() & ~3); 368 369 // check permissions for this access 370 if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) { 371 // instruction access fault 372 fault(req->vaddr, req->xc); 373 acv++; 374 return ITB_Acv_Fault; 375 } 376 377 hits++; 378 } 379 } 380 381 // check that the physical address is ok (catch bad physical addresses) 382 if (req->paddr & ~PAddrImplMask) 383 return Machine_Check_Fault; 384 385 checkCacheability(req); 386 387 return No_Fault; 388} 389 390/////////////////////////////////////////////////////////////////////// 391// 392// Alpha DTB 393// 394AlphaDTB::AlphaDTB(const std::string &name, int size) 395 : AlphaTLB(name, size) 396{} 397 398void 399AlphaDTB::regStats() 400{ 401 read_hits 402 .name(name() + ".read_hits") 403 .desc("DTB read hits") 404 ; 405 406 read_misses 407 .name(name() + ".read_misses") 408 .desc("DTB read misses") 409 ; 410 411 read_acv 412 .name(name() + ".read_acv") 413 .desc("DTB read access violations") 414 ; 415 416 read_accesses 417 .name(name() + ".read_accesses") 418 .desc("DTB read accesses") 419 ; 420 421 write_hits 422 .name(name() + ".write_hits") 423 .desc("DTB write hits") 424 ; 425 426 write_misses 427 .name(name() + ".write_misses") 428 .desc("DTB write misses") 429 ; 430 431 write_acv 432 .name(name() + ".write_acv") 433 .desc("DTB write access violations") 434 ; 435 436 write_accesses 437 .name(name() + ".write_accesses") 438 .desc("DTB write accesses") 439 ; 440 441 hits 442 .name(name() + ".hits") 443 .desc("DTB hits") 444 ; 445 446 misses 447 .name(name() + ".misses") 448 .desc("DTB misses") 449 ; 450 451 acv 452 .name(name() + ".acv") 453 .desc("DTB access violations") 454 ; 455 456 accesses 457 .name(name() + ".accesses") 458 .desc("DTB accesses") 459 ; 460 461 hits = read_hits + write_hits; 462 misses = read_misses + write_misses; 463 acv = read_acv + write_acv; 464 accesses = read_accesses + write_accesses; 465} 466 467void 468AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const 469{ 470 ExecContext *xc = req->xc; 471 AlphaISA::VAddr vaddr = req->vaddr; 472 uint64_t *ipr = xc->regs.ipr; 473 474 // Set fault address and flags. Even though we're modeling an 475 // EV5, we use the EV6 technique of not latching fault registers 476 // on VPTE loads (instead of locking the registers until IPR_VA is 477 // read, like the EV5). The EV6 approach is cleaner and seems to 478 // work with EV5 PAL code, but not the other way around. 479 if (!xc->misspeculating() 480 && !(req->flags & VPTE) && !(req->flags & NO_FAULT)) { 481 // set VA register with faulting address 482 ipr[AlphaISA::IPR_VA] = req->vaddr; 483 484 // set MM_STAT register flags 485 ipr[AlphaISA::IPR_MM_STAT] = 486 (((Opcode(xc->getInst()) & 0x3f) << 11) 487 | ((Ra(xc->getInst()) & 0x1f) << 6) 488 | (flags & 0x3f)); 489 490 // set VA_FORM register with faulting formatted address 491 ipr[AlphaISA::IPR_VA_FORM] = 492 ipr[AlphaISA::IPR_MVPTBR] | (vaddr.vpn() << 3); 493 } 494} 495 496Fault 497AlphaDTB::translate(MemReqPtr &req, bool write) const 498{ 499 RegFile *regs = &req->xc->regs; 500 Addr pc = regs->pc; 501 InternalProcReg *ipr = regs->ipr; 502 503 AlphaISA::mode_type mode = 504 (AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]); 505 506 507 /** 508 * Check for alignment faults 509 */ 510 if (req->vaddr & (req->size - 1)) { 511 fault(req, write ? MM_STAT_WR_MASK : 0); 512 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr, 513 req->size); 514 return Alignment_Fault; 515 } 516 517 if (pc & 0x1) { 518 mode = (req->flags & ALTMODE) ? 519 (AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE]) 520 : AlphaISA::mode_kernel; 521 } 522 523 if (req->flags & PHYSICAL) { 524 req->paddr = req->vaddr; 525 } else { 526 // verify that this is a good virtual address 527 if (!validVirtualAddress(req->vaddr)) { 528 fault(req, (write ? MM_STAT_WR_MASK : 0) | 529 MM_STAT_BAD_VA_MASK | 530 MM_STAT_ACV_MASK); 531 532 if (write) { write_acv++; } else { read_acv++; } 533 return DTB_Fault_Fault; 534 } 535 536 // Check for "superpage" mapping 537#if ALPHA_TLASER 538 if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && 539 VAddrSpaceEV5(req->vaddr) == 2) { 540#else 541 if (VAddrSpaceEV6(req->vaddr) == 0x7e) { 542#endif 543 544 // only valid in kernel mode 545 if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) != 546 AlphaISA::mode_kernel) { 547 fault(req, ((write ? MM_STAT_WR_MASK : 0) | 548 MM_STAT_ACV_MASK)); 549 if (write) { write_acv++; } else { read_acv++; } 550 return DTB_Acv_Fault; 551 } 552 553 req->paddr = req->vaddr & PAddrImplMask; 554 555#if !ALPHA_TLASER 556 // sign extend the physical address properly 557 if (req->paddr & PAddrUncachedBit40) 558 req->paddr |= ULL(0xf0000000000); 559 else 560 req->paddr &= ULL(0xffffffffff); 561#endif 562 563 } else { 564 if (write) 565 write_accesses++; 566 else 567 read_accesses++; 568 569 // not a physical address: need to look up pte 570 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(), 571 DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); 572 573 if (!pte) { 574 // page fault 575 fault(req, (write ? MM_STAT_WR_MASK : 0) | 576 MM_STAT_DTB_MISS_MASK); 577 if (write) { write_misses++; } else { read_misses++; } 578 return (req->flags & VPTE) ? Pdtb_Miss_Fault : Ndtb_Miss_Fault; 579 } 580 581 req->paddr = (pte->ppn << AlphaISA::PageShift) + 582 AlphaISA::VAddr(req->vaddr).offset(); 583 584 if (write) { 585 if (!(pte->xwe & MODE2MASK(mode))) { 586 // declare the instruction access fault 587 fault(req, MM_STAT_WR_MASK | 588 MM_STAT_ACV_MASK | 589 (pte->fonw ? MM_STAT_FONW_MASK : 0)); 590 write_acv++; 591 return DTB_Fault_Fault; 592 } 593 if (pte->fonw) { 594 fault(req, MM_STAT_WR_MASK | 595 MM_STAT_FONW_MASK); 596 write_acv++; 597 return DTB_Fault_Fault; 598 } 599 } else { 600 if (!(pte->xre & MODE2MASK(mode))) { 601 fault(req, MM_STAT_ACV_MASK | 602 (pte->fonr ? MM_STAT_FONR_MASK : 0)); 603 read_acv++; 604 return DTB_Acv_Fault; 605 } 606 if (pte->fonr) { 607 fault(req, MM_STAT_FONR_MASK); 608 read_acv++; 609 return DTB_Fault_Fault; 610 } 611 } 612 } 613 614 if (write) 615 write_hits++; 616 else 617 read_hits++; 618 } 619 620 // check that the physical address is ok (catch bad physical addresses) 621 if (req->paddr & ~PAddrImplMask) 622 return Machine_Check_Fault; 623 624 checkCacheability(req); 625 626 return No_Fault; 627} 628 629AlphaISA::PTE & 630AlphaTLB::index(bool advance) 631{ 632 AlphaISA::PTE *pte = &table[nlu]; 633 634 if (advance) 635 nextnlu(); 636 637 return *pte; 638} 639 640DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB) 641 642BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) 643 644 Param<int> size; 645 646END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) 647 648BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB) 649 650 INIT_PARAM_DFLT(size, "TLB size", 48) 651 652END_INIT_SIM_OBJECT_PARAMS(AlphaITB) 653 654 655CREATE_SIM_OBJECT(AlphaITB) 656{ 657 return new AlphaITB(getInstanceName(), size); 658} 659 660REGISTER_SIM_OBJECT("AlphaITB", AlphaITB) 661 662BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) 663 664 Param<int> size; 665 666END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) 667 668BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB) 669 670 INIT_PARAM_DFLT(size, "TLB size", 64) 671 672END_INIT_SIM_OBJECT_PARAMS(AlphaDTB) 673 674 675CREATE_SIM_OBJECT(AlphaDTB) 676{ 677 return new AlphaDTB(getInstanceName(), size); 678} 679 680REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB) 681 682