tlb.cc revision 1858 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sstream>
30#include <string>
31#include <vector>
32
33#include "arch/alpha/alpha_memory.hh"
34#include "base/inifile.hh"
35#include "base/str.hh"
36#include "base/trace.hh"
37#include "config/alpha_tlaser.hh"
38#include "cpu/exec_context.hh"
39#include "sim/builder.hh"
40
41using namespace std;
42using namespace EV5;
43
44///////////////////////////////////////////////////////////////////////
45//
46//  Alpha TLB
47//
48#ifdef DEBUG
49bool uncacheBit39 = false;
50bool uncacheBit40 = false;
51#endif
52
53#define MODE2MASK(X)			(1 << (X))
54
55AlphaTLB::AlphaTLB(const string &name, int s)
56    : SimObject(name), size(s), nlu(0)
57{
58    table = new AlphaISA::PTE[size];
59    memset(table, 0, sizeof(AlphaISA::PTE[size]));
60}
61
62AlphaTLB::~AlphaTLB()
63{
64    if (table)
65        delete [] table;
66}
67
68// look up an entry in the TLB
69AlphaISA::PTE *
70AlphaTLB::lookup(Addr vpn, uint8_t asn) const
71{
72    // assume not found...
73    AlphaISA::PTE *retval = NULL;
74
75    PageTable::const_iterator i = lookupTable.find(vpn);
76    if (i != lookupTable.end()) {
77        while (i->first == vpn) {
78            int index = i->second;
79            AlphaISA::PTE *pte = &table[index];
80            assert(pte->valid);
81            if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
82                retval = pte;
83                break;
84            }
85
86            ++i;
87        }
88    }
89
90    DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
91            retval ? "hit" : "miss", retval ? retval->ppn : 0);
92    return retval;
93}
94
95
96void
97AlphaTLB::checkCacheability(MemReqPtr &req)
98{
99    // in Alpha, cacheability is controlled by upper-level bits of the
100    // physical address
101
102    /*
103     * We support having the uncacheable bit in either bit 39 or bit 40.
104     * The Turbolaser platform (and EV5) support having the bit in 39, but
105     * Tsunami (which Linux assumes uses an EV6) generates accesses with
106     * the bit in 40.  So we must check for both, but we have debug flags
107     * to catch a weird case where both are used, which shouldn't happen.
108     */
109
110
111#if ALPHA_TLASER
112    if (req->paddr & PAddrUncachedBit39) {
113#else
114    if (req->paddr & PAddrUncachedBit43) {
115#endif
116        // IPR memory space not implemented
117        if (PAddrIprSpace(req->paddr)) {
118            if (!req->xc->misspeculating()) {
119                switch (req->paddr) {
120                  case ULL(0xFFFFF00188):
121                    req->data = 0;
122                    break;
123
124                  default:
125                    panic("IPR memory space not implemented! PA=%x\n",
126                          req->paddr);
127                }
128            }
129        } else {
130            // mark request as uncacheable
131            req->flags |= UNCACHEABLE;
132
133#if !ALPHA_TLASER
134            // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
135            req->paddr &= PAddrUncachedMask;
136#endif
137        }
138    }
139}
140
141
142// insert a new TLB entry
143void
144AlphaTLB::insert(Addr addr, AlphaISA::PTE &pte)
145{
146    AlphaISA::VAddr vaddr = addr;
147    if (table[nlu].valid) {
148        Addr oldvpn = table[nlu].tag;
149        PageTable::iterator i = lookupTable.find(oldvpn);
150
151        if (i == lookupTable.end())
152            panic("TLB entry not found in lookupTable");
153
154        int index;
155        while ((index = i->second) != nlu) {
156            if (table[index].tag != oldvpn)
157                panic("TLB entry not found in lookupTable");
158
159            ++i;
160        }
161
162        DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
163
164        lookupTable.erase(i);
165    }
166
167    DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
168
169    table[nlu] = pte;
170    table[nlu].tag = vaddr.vpn();
171    table[nlu].valid = true;
172
173    lookupTable.insert(make_pair(vaddr.vpn(), nlu));
174    nextnlu();
175}
176
177void
178AlphaTLB::flushAll()
179{
180    memset(table, 0, sizeof(AlphaISA::PTE[size]));
181    lookupTable.clear();
182    nlu = 0;
183}
184
185void
186AlphaTLB::flushProcesses()
187{
188    PageTable::iterator i = lookupTable.begin();
189    PageTable::iterator end = lookupTable.end();
190    while (i != end) {
191        int index = i->second;
192        AlphaISA::PTE *pte = &table[index];
193        assert(pte->valid);
194
195        if (!pte->asma) {
196            DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
197            pte->valid = false;
198            lookupTable.erase(i);
199        }
200
201        ++i;
202    }
203}
204
205void
206AlphaTLB::flushAddr(Addr addr, uint8_t asn)
207{
208    AlphaISA::VAddr vaddr = addr;
209
210    PageTable::iterator i = lookupTable.find(vaddr.vpn());
211    if (i == lookupTable.end())
212        return;
213
214    while (i->first == vaddr.vpn()) {
215        int index = i->second;
216        AlphaISA::PTE *pte = &table[index];
217        assert(pte->valid);
218
219        if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) {
220            DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
221                    pte->ppn);
222
223            // invalidate this entry
224            pte->valid = false;
225
226            lookupTable.erase(i);
227        }
228
229        ++i;
230    }
231}
232
233
234void
235AlphaTLB::serialize(ostream &os)
236{
237    SERIALIZE_SCALAR(size);
238    SERIALIZE_SCALAR(nlu);
239
240    for (int i = 0; i < size; i++) {
241        nameOut(os, csprintf("%s.PTE%d", name(), i));
242        table[i].serialize(os);
243    }
244}
245
246void
247AlphaTLB::unserialize(Checkpoint *cp, const string &section)
248{
249    UNSERIALIZE_SCALAR(size);
250    UNSERIALIZE_SCALAR(nlu);
251
252    for (int i = 0; i < size; i++) {
253        table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
254        if (table[i].valid) {
255            lookupTable.insert(make_pair(table[i].tag, i));
256        }
257    }
258}
259
260
261///////////////////////////////////////////////////////////////////////
262//
263//  Alpha ITB
264//
265AlphaITB::AlphaITB(const std::string &name, int size)
266    : AlphaTLB(name, size)
267{}
268
269
270void
271AlphaITB::regStats()
272{
273    hits
274        .name(name() + ".hits")
275        .desc("ITB hits");
276    misses
277        .name(name() + ".misses")
278        .desc("ITB misses");
279    acv
280        .name(name() + ".acv")
281        .desc("ITB acv");
282    accesses
283        .name(name() + ".accesses")
284        .desc("ITB accesses");
285
286    accesses = hits + misses;
287}
288
289void
290AlphaITB::fault(Addr pc, ExecContext *xc) const
291{
292    uint64_t *ipr = xc->regs.ipr;
293
294    if (!xc->misspeculating()) {
295        ipr[AlphaISA::IPR_ITB_TAG] = pc;
296        ipr[AlphaISA::IPR_IFAULT_VA_FORM] =
297            ipr[AlphaISA::IPR_IVPTBR] | (AlphaISA::VAddr(pc).vpn() << 3);
298    }
299}
300
301
302Fault
303AlphaITB::translate(MemReqPtr &req) const
304{
305    InternalProcReg *ipr = req->xc->regs.ipr;
306
307    if (AlphaISA::PcPAL(req->vaddr)) {
308        // strip off PAL PC marker (lsb is 1)
309        req->paddr = (req->vaddr & ~3) & PAddrImplMask;
310        hits++;
311        return No_Fault;
312    }
313
314    if (req->flags & PHYSICAL) {
315        req->paddr = req->vaddr;
316    } else {
317        // verify that this is a good virtual address
318        if (!validVirtualAddress(req->vaddr)) {
319            fault(req->vaddr, req->xc);
320            acv++;
321            return ITB_Acv_Fault;
322        }
323
324
325        // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
326        // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
327#if ALPHA_TLASER
328        if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
329            VAddrSpaceEV5(req->vaddr) == 2) {
330#else
331        if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
332#endif
333            // only valid in kernel mode
334            if (ICM_CM(ipr[AlphaISA::IPR_ICM]) !=
335                AlphaISA::mode_kernel) {
336                fault(req->vaddr, req->xc);
337                acv++;
338                return ITB_Acv_Fault;
339            }
340
341            req->paddr = req->vaddr & PAddrImplMask;
342
343#if !ALPHA_TLASER
344            // sign extend the physical address properly
345            if (req->paddr & PAddrUncachedBit40)
346                req->paddr |= ULL(0xf0000000000);
347            else
348                req->paddr &= ULL(0xffffffffff);
349#endif
350
351        } else {
352            // not a physical address: need to look up pte
353            AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
354                                        DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
355
356            if (!pte) {
357                fault(req->vaddr, req->xc);
358                misses++;
359                return ITB_Fault_Fault;
360            }
361
362            req->paddr = (pte->ppn << AlphaISA::PageShift) +
363                (AlphaISA::VAddr(req->vaddr).offset() & ~3);
364
365            // check permissions for this access
366            if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) {
367                // instruction access fault
368                fault(req->vaddr, req->xc);
369                acv++;
370                return ITB_Acv_Fault;
371            }
372
373            hits++;
374        }
375    }
376
377    // check that the physical address is ok (catch bad physical addresses)
378    if (req->paddr & ~PAddrImplMask)
379        return Machine_Check_Fault;
380
381    checkCacheability(req);
382
383    return No_Fault;
384}
385
386///////////////////////////////////////////////////////////////////////
387//
388//  Alpha DTB
389//
390AlphaDTB::AlphaDTB(const std::string &name, int size)
391    : AlphaTLB(name, size)
392{}
393
394void
395AlphaDTB::regStats()
396{
397    read_hits
398        .name(name() + ".read_hits")
399        .desc("DTB read hits")
400        ;
401
402    read_misses
403        .name(name() + ".read_misses")
404        .desc("DTB read misses")
405        ;
406
407    read_acv
408        .name(name() + ".read_acv")
409        .desc("DTB read access violations")
410        ;
411
412    read_accesses
413        .name(name() + ".read_accesses")
414        .desc("DTB read accesses")
415        ;
416
417    write_hits
418        .name(name() + ".write_hits")
419        .desc("DTB write hits")
420        ;
421
422    write_misses
423        .name(name() + ".write_misses")
424        .desc("DTB write misses")
425        ;
426
427    write_acv
428        .name(name() + ".write_acv")
429        .desc("DTB write access violations")
430        ;
431
432    write_accesses
433        .name(name() + ".write_accesses")
434        .desc("DTB write accesses")
435        ;
436
437    hits
438        .name(name() + ".hits")
439        .desc("DTB hits")
440        ;
441
442    misses
443        .name(name() + ".misses")
444        .desc("DTB misses")
445        ;
446
447    acv
448        .name(name() + ".acv")
449        .desc("DTB access violations")
450        ;
451
452    accesses
453        .name(name() + ".accesses")
454        .desc("DTB accesses")
455        ;
456
457    hits = read_hits + write_hits;
458    misses = read_misses + write_misses;
459    acv = read_acv + write_acv;
460    accesses = read_accesses + write_accesses;
461}
462
463void
464AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
465{
466    ExecContext *xc = req->xc;
467    AlphaISA::VAddr vaddr = req->vaddr;
468    uint64_t *ipr = xc->regs.ipr;
469
470    // Set fault address and flags.  Even though we're modeling an
471    // EV5, we use the EV6 technique of not latching fault registers
472    // on VPTE loads (instead of locking the registers until IPR_VA is
473    // read, like the EV5).  The EV6 approach is cleaner and seems to
474    // work with EV5 PAL code, but not the other way around.
475    if (!xc->misspeculating()
476        && !(req->flags & VPTE) && !(req->flags & NO_FAULT)) {
477        // set VA register with faulting address
478        ipr[AlphaISA::IPR_VA] = req->vaddr;
479
480        // set MM_STAT register flags
481        ipr[AlphaISA::IPR_MM_STAT] =
482            (((Opcode(xc->getInst()) & 0x3f) << 11)
483             | ((Ra(xc->getInst()) & 0x1f) << 6)
484             | (flags & 0x3f));
485
486        // set VA_FORM register with faulting formatted address
487        ipr[AlphaISA::IPR_VA_FORM] =
488            ipr[AlphaISA::IPR_MVPTBR] | (vaddr.vpn() << 3);
489    }
490}
491
492Fault
493AlphaDTB::translate(MemReqPtr &req, bool write) const
494{
495    RegFile *regs = &req->xc->regs;
496    Addr pc = regs->pc;
497    InternalProcReg *ipr = regs->ipr;
498
499    AlphaISA::mode_type mode =
500        (AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]);
501
502
503    /**
504     * Check for alignment faults
505     */
506    if (req->vaddr & (req->size - 1)) {
507        fault(req, write ? MM_STAT_WR_MASK : 0);
508        DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
509                req->size);
510        return Alignment_Fault;
511    }
512
513    if (pc & 0x1) {
514        mode = (req->flags & ALTMODE) ?
515            (AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE])
516            : AlphaISA::mode_kernel;
517    }
518
519    if (req->flags & PHYSICAL) {
520        req->paddr = req->vaddr;
521    } else {
522        // verify that this is a good virtual address
523        if (!validVirtualAddress(req->vaddr)) {
524            fault(req, (write ? MM_STAT_WR_MASK : 0) |
525                  MM_STAT_BAD_VA_MASK |
526                  MM_STAT_ACV_MASK);
527
528            if (write) { write_acv++; } else { read_acv++; }
529            return DTB_Fault_Fault;
530        }
531
532        // Check for "superpage" mapping
533#if ALPHA_TLASER
534        if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
535            VAddrSpaceEV5(req->vaddr) == 2) {
536#else
537        if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
538#endif
539
540            // only valid in kernel mode
541            if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
542                AlphaISA::mode_kernel) {
543                fault(req, ((write ? MM_STAT_WR_MASK : 0) |
544                            MM_STAT_ACV_MASK));
545                if (write) { write_acv++; } else { read_acv++; }
546                return DTB_Acv_Fault;
547            }
548
549            req->paddr = req->vaddr & PAddrImplMask;
550
551#if !ALPHA_TLASER
552            // sign extend the physical address properly
553            if (req->paddr & PAddrUncachedBit40)
554                req->paddr |= ULL(0xf0000000000);
555            else
556                req->paddr &= ULL(0xffffffffff);
557#endif
558
559        } else {
560            if (write)
561                write_accesses++;
562            else
563                read_accesses++;
564
565            // not a physical address: need to look up pte
566            AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
567                                        DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
568
569            if (!pte) {
570                // page fault
571                fault(req, (write ? MM_STAT_WR_MASK : 0) |
572                      MM_STAT_DTB_MISS_MASK);
573                if (write) { write_misses++; } else { read_misses++; }
574                return (req->flags & VPTE) ? Pdtb_Miss_Fault : Ndtb_Miss_Fault;
575            }
576
577            req->paddr = (pte->ppn << AlphaISA::PageShift) +
578                AlphaISA::VAddr(req->vaddr).offset();
579
580            if (write) {
581                if (!(pte->xwe & MODE2MASK(mode))) {
582                    // declare the instruction access fault
583                    fault(req, MM_STAT_WR_MASK |
584                          MM_STAT_ACV_MASK |
585                          (pte->fonw ? MM_STAT_FONW_MASK : 0));
586                    write_acv++;
587                    return DTB_Fault_Fault;
588                }
589                if (pte->fonw) {
590                    fault(req, MM_STAT_WR_MASK |
591                          MM_STAT_FONW_MASK);
592                    write_acv++;
593                    return DTB_Fault_Fault;
594                }
595            } else {
596                if (!(pte->xre & MODE2MASK(mode))) {
597                    fault(req, MM_STAT_ACV_MASK |
598                          (pte->fonr ? MM_STAT_FONR_MASK : 0));
599                    read_acv++;
600                    return DTB_Acv_Fault;
601                }
602                if (pte->fonr) {
603                    fault(req, MM_STAT_FONR_MASK);
604                    read_acv++;
605                    return DTB_Fault_Fault;
606                }
607            }
608        }
609
610        if (write)
611            write_hits++;
612        else
613            read_hits++;
614    }
615
616    // check that the physical address is ok (catch bad physical addresses)
617    if (req->paddr & ~PAddrImplMask)
618        return Machine_Check_Fault;
619
620    checkCacheability(req);
621
622    return No_Fault;
623}
624
625AlphaISA::PTE &
626AlphaTLB::index(bool advance)
627{
628    AlphaISA::PTE *pte = &table[nlu];
629
630    if (advance)
631        nextnlu();
632
633    return *pte;
634}
635
636DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB)
637
638BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
639
640    Param<int> size;
641
642END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
643
644BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB)
645
646    INIT_PARAM_DFLT(size, "TLB size", 48)
647
648END_INIT_SIM_OBJECT_PARAMS(AlphaITB)
649
650
651CREATE_SIM_OBJECT(AlphaITB)
652{
653    return new AlphaITB(getInstanceName(), size);
654}
655
656REGISTER_SIM_OBJECT("AlphaITB", AlphaITB)
657
658BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
659
660    Param<int> size;
661
662END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
663
664BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
665
666    INIT_PARAM_DFLT(size, "TLB size", 64)
667
668END_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
669
670
671CREATE_SIM_OBJECT(AlphaDTB)
672{
673    return new AlphaDTB(getInstanceName(), size);
674}
675
676REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB)
677
678