tlb.cc revision 11320
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Andrew Schultz 312SN/A */ 322SN/A 3310905Sandreas.sandberg@arm.com#include "arch/alpha/tlb.hh" 3410905Sandreas.sandberg@arm.com 3510905Sandreas.sandberg@arm.com#include <algorithm> 3610474Sandreas.hansson@arm.com#include <memory> 372SN/A#include <string> 382SN/A#include <vector> 392SN/A 408229Snate@binkert.org#include "arch/alpha/faults.hh" 412984Sgblack@eecs.umich.edu#include "arch/alpha/pagetable.hh" 428591Sgblack@eecs.umich.edu#include "arch/generic/debugfaults.hh" 43146SN/A#include "base/inifile.hh" 44146SN/A#include "base/str.hh" 45146SN/A#include "base/trace.hh" 462680Sktlim@umich.edu#include "cpu/thread_context.hh" 478232Snate@binkert.org#include "debug/TLB.hh" 488738Sgblack@eecs.umich.edu#include "sim/full_system.hh" 492SN/A 502SN/Ausing namespace std; 512SN/A 524088Sbinkertn@umich.edunamespace AlphaISA { 535569Snate@binkert.org 543838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 553838Shsul@eecs.umich.edu// 563838Shsul@eecs.umich.edu// Alpha TLB 573838Shsul@eecs.umich.edu// 585569Snate@binkert.org 59860SN/A#ifdef DEBUG 603838Shsul@eecs.umich.edubool uncacheBit39 = false; 613838Shsul@eecs.umich.edubool uncacheBit40 = false; 62860SN/A#endif 63860SN/A 645569Snate@binkert.org#define MODE2MASK(X) (1 << (X)) 651147SN/A 665034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 6710905Sandreas.sandberg@arm.com : BaseTLB(p), table(p->size), nlu(0) 683838Shsul@eecs.umich.edu{ 694957Sacolyte@umich.edu flushCache(); 703838Shsul@eecs.umich.edu} 712SN/A 723838Shsul@eecs.umich.eduTLB::~TLB() 733838Shsul@eecs.umich.edu{ 743838Shsul@eecs.umich.edu} 752SN/A 766022Sgblack@eecs.umich.eduvoid 776022Sgblack@eecs.umich.eduTLB::regStats() 786022Sgblack@eecs.umich.edu{ 796022Sgblack@eecs.umich.edu fetch_hits 806022Sgblack@eecs.umich.edu .name(name() + ".fetch_hits") 816022Sgblack@eecs.umich.edu .desc("ITB hits"); 826022Sgblack@eecs.umich.edu fetch_misses 836022Sgblack@eecs.umich.edu .name(name() + ".fetch_misses") 846022Sgblack@eecs.umich.edu .desc("ITB misses"); 856022Sgblack@eecs.umich.edu fetch_acv 866022Sgblack@eecs.umich.edu .name(name() + ".fetch_acv") 876022Sgblack@eecs.umich.edu .desc("ITB acv"); 886022Sgblack@eecs.umich.edu fetch_accesses 896022Sgblack@eecs.umich.edu .name(name() + ".fetch_accesses") 906022Sgblack@eecs.umich.edu .desc("ITB accesses"); 916022Sgblack@eecs.umich.edu 926022Sgblack@eecs.umich.edu fetch_accesses = fetch_hits + fetch_misses; 936022Sgblack@eecs.umich.edu 946022Sgblack@eecs.umich.edu read_hits 956022Sgblack@eecs.umich.edu .name(name() + ".read_hits") 966022Sgblack@eecs.umich.edu .desc("DTB read hits") 976022Sgblack@eecs.umich.edu ; 986022Sgblack@eecs.umich.edu 996022Sgblack@eecs.umich.edu read_misses 1006022Sgblack@eecs.umich.edu .name(name() + ".read_misses") 1016022Sgblack@eecs.umich.edu .desc("DTB read misses") 1026022Sgblack@eecs.umich.edu ; 1036022Sgblack@eecs.umich.edu 1046022Sgblack@eecs.umich.edu read_acv 1056022Sgblack@eecs.umich.edu .name(name() + ".read_acv") 1066022Sgblack@eecs.umich.edu .desc("DTB read access violations") 1076022Sgblack@eecs.umich.edu ; 1086022Sgblack@eecs.umich.edu 1096022Sgblack@eecs.umich.edu read_accesses 1106022Sgblack@eecs.umich.edu .name(name() + ".read_accesses") 1116022Sgblack@eecs.umich.edu .desc("DTB read accesses") 1126022Sgblack@eecs.umich.edu ; 1136022Sgblack@eecs.umich.edu 1146022Sgblack@eecs.umich.edu write_hits 1156022Sgblack@eecs.umich.edu .name(name() + ".write_hits") 1166022Sgblack@eecs.umich.edu .desc("DTB write hits") 1176022Sgblack@eecs.umich.edu ; 1186022Sgblack@eecs.umich.edu 1196022Sgblack@eecs.umich.edu write_misses 1206022Sgblack@eecs.umich.edu .name(name() + ".write_misses") 1216022Sgblack@eecs.umich.edu .desc("DTB write misses") 1226022Sgblack@eecs.umich.edu ; 1236022Sgblack@eecs.umich.edu 1246022Sgblack@eecs.umich.edu write_acv 1256022Sgblack@eecs.umich.edu .name(name() + ".write_acv") 1266022Sgblack@eecs.umich.edu .desc("DTB write access violations") 1276022Sgblack@eecs.umich.edu ; 1286022Sgblack@eecs.umich.edu 1296022Sgblack@eecs.umich.edu write_accesses 1306022Sgblack@eecs.umich.edu .name(name() + ".write_accesses") 1316022Sgblack@eecs.umich.edu .desc("DTB write accesses") 1326022Sgblack@eecs.umich.edu ; 1336022Sgblack@eecs.umich.edu 1346022Sgblack@eecs.umich.edu data_hits 1356022Sgblack@eecs.umich.edu .name(name() + ".data_hits") 1366022Sgblack@eecs.umich.edu .desc("DTB hits") 1376022Sgblack@eecs.umich.edu ; 1386022Sgblack@eecs.umich.edu 1396022Sgblack@eecs.umich.edu data_misses 1406022Sgblack@eecs.umich.edu .name(name() + ".data_misses") 1416022Sgblack@eecs.umich.edu .desc("DTB misses") 1426022Sgblack@eecs.umich.edu ; 1436022Sgblack@eecs.umich.edu 1446022Sgblack@eecs.umich.edu data_acv 1456022Sgblack@eecs.umich.edu .name(name() + ".data_acv") 1466022Sgblack@eecs.umich.edu .desc("DTB access violations") 1476022Sgblack@eecs.umich.edu ; 1486022Sgblack@eecs.umich.edu 1496022Sgblack@eecs.umich.edu data_accesses 1506022Sgblack@eecs.umich.edu .name(name() + ".data_accesses") 1516022Sgblack@eecs.umich.edu .desc("DTB accesses") 1526022Sgblack@eecs.umich.edu ; 1536022Sgblack@eecs.umich.edu 1546022Sgblack@eecs.umich.edu data_hits = read_hits + write_hits; 1556022Sgblack@eecs.umich.edu data_misses = read_misses + write_misses; 1566022Sgblack@eecs.umich.edu data_acv = read_acv + write_acv; 1576022Sgblack@eecs.umich.edu data_accesses = read_accesses + write_accesses; 1586022Sgblack@eecs.umich.edu} 1596022Sgblack@eecs.umich.edu 1603838Shsul@eecs.umich.edu// look up an entry in the TLB 1615004Sgblack@eecs.umich.eduTlbEntry * 1624967Sacolyte@umich.eduTLB::lookup(Addr vpn, uint8_t asn) 1633838Shsul@eecs.umich.edu{ 1643838Shsul@eecs.umich.edu // assume not found... 1655004Sgblack@eecs.umich.edu TlbEntry *retval = NULL; 1662SN/A 1675004Sgblack@eecs.umich.edu if (EntryCache[0]) { 1685004Sgblack@eecs.umich.edu if (vpn == EntryCache[0]->tag && 1695004Sgblack@eecs.umich.edu (EntryCache[0]->asma || EntryCache[0]->asn == asn)) 1705004Sgblack@eecs.umich.edu retval = EntryCache[0]; 1715004Sgblack@eecs.umich.edu else if (EntryCache[1]) { 1725004Sgblack@eecs.umich.edu if (vpn == EntryCache[1]->tag && 1735004Sgblack@eecs.umich.edu (EntryCache[1]->asma || EntryCache[1]->asn == asn)) 1745004Sgblack@eecs.umich.edu retval = EntryCache[1]; 1755004Sgblack@eecs.umich.edu else if (EntryCache[2] && vpn == EntryCache[2]->tag && 1765004Sgblack@eecs.umich.edu (EntryCache[2]->asma || EntryCache[2]->asn == asn)) 1775004Sgblack@eecs.umich.edu retval = EntryCache[2]; 1784962Sacolyte@umich.edu } 1794962Sacolyte@umich.edu } 1804962Sacolyte@umich.edu 1814967Sacolyte@umich.edu if (retval == NULL) { 1824957Sacolyte@umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 1834957Sacolyte@umich.edu if (i != lookupTable.end()) { 1844957Sacolyte@umich.edu while (i->first == vpn) { 1854957Sacolyte@umich.edu int index = i->second; 1865004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 1875004Sgblack@eecs.umich.edu assert(entry->valid); 1885004Sgblack@eecs.umich.edu if (vpn == entry->tag && (entry->asma || entry->asn == asn)) { 1895004Sgblack@eecs.umich.edu retval = updateCache(entry); 1904957Sacolyte@umich.edu break; 1914957Sacolyte@umich.edu } 1924957Sacolyte@umich.edu 1934957Sacolyte@umich.edu ++i; 1941413SN/A } 1951413SN/A } 1962SN/A } 1972SN/A 1983838Shsul@eecs.umich.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 1993838Shsul@eecs.umich.edu retval ? "hit" : "miss", retval ? retval->ppn : 0); 2003838Shsul@eecs.umich.edu return retval; 2013838Shsul@eecs.umich.edu} 2022SN/A 2033838Shsul@eecs.umich.eduFault 2045532Ssaidi@eecs.umich.eduTLB::checkCacheability(RequestPtr &req, bool itb) 2053838Shsul@eecs.umich.edu{ 2065569Snate@binkert.org // in Alpha, cacheability is controlled by upper-level bits of the 2075569Snate@binkert.org // physical address 2083838Shsul@eecs.umich.edu 2095569Snate@binkert.org /* 2105569Snate@binkert.org * We support having the uncacheable bit in either bit 39 or bit 2115569Snate@binkert.org * 40. The Turbolaser platform (and EV5) support having the bit 2125569Snate@binkert.org * in 39, but Tsunami (which Linux assumes uses an EV6) generates 2135569Snate@binkert.org * accesses with the bit in 40. So we must check for both, but we 2145569Snate@binkert.org * have debug flags to catch a weird case where both are used, 2155569Snate@binkert.org * which shouldn't happen. 2165569Snate@binkert.org */ 2173838Shsul@eecs.umich.edu 2183838Shsul@eecs.umich.edu 2196025Snate@binkert.org if (req->getPaddr() & PAddrUncachedBit43) { 2203838Shsul@eecs.umich.edu // IPR memory space not implemented 2213838Shsul@eecs.umich.edu if (PAddrIprSpace(req->getPaddr())) { 22210474Sandreas.hansson@arm.com return std::make_shared<UnimpFault>( 22310474Sandreas.hansson@arm.com "IPR memory space not implemented!"); 2243838Shsul@eecs.umich.edu } else { 2253838Shsul@eecs.umich.edu // mark request as uncacheable 22610824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 2273838Shsul@eecs.umich.edu 2285569Snate@binkert.org // Clear bits 42:35 of the physical address (10-2 in 2295569Snate@binkert.org // Tsunami manual) 2303838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & PAddrUncachedMask); 231924SN/A } 2325532Ssaidi@eecs.umich.edu // We shouldn't be able to read from an uncachable address in Alpha as 23311320Ssteve.reinhardt@amd.com // we don't have a ROM and we don't want to try to fetch from a device 23411320Ssteve.reinhardt@amd.com // register as we destroy any data that is clear-on-read. 23511320Ssteve.reinhardt@amd.com if (req->isUncacheable() && itb) 23610474Sandreas.hansson@arm.com return std::make_shared<UnimpFault>( 23710474Sandreas.hansson@arm.com "CPU trying to fetch from uncached I/O"); 2385532Ssaidi@eecs.umich.edu 2392SN/A } 2403838Shsul@eecs.umich.edu return NoFault; 2413838Shsul@eecs.umich.edu} 2422SN/A 2432SN/A 2443838Shsul@eecs.umich.edu// insert a new TLB entry 2453838Shsul@eecs.umich.eduvoid 2465004Sgblack@eecs.umich.eduTLB::insert(Addr addr, TlbEntry &entry) 2473838Shsul@eecs.umich.edu{ 2484957Sacolyte@umich.edu flushCache(); 2493838Shsul@eecs.umich.edu VAddr vaddr = addr; 2503838Shsul@eecs.umich.edu if (table[nlu].valid) { 2513838Shsul@eecs.umich.edu Addr oldvpn = table[nlu].tag; 2523838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(oldvpn); 2533838Shsul@eecs.umich.edu 2543838Shsul@eecs.umich.edu if (i == lookupTable.end()) 2553838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 2563838Shsul@eecs.umich.edu 2573838Shsul@eecs.umich.edu int index; 2583838Shsul@eecs.umich.edu while ((index = i->second) != nlu) { 2593838Shsul@eecs.umich.edu if (table[index].tag != oldvpn) 2603838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 2613838Shsul@eecs.umich.edu 2623838Shsul@eecs.umich.edu ++i; 2633838Shsul@eecs.umich.edu } 2643838Shsul@eecs.umich.edu 2653838Shsul@eecs.umich.edu DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 2663838Shsul@eecs.umich.edu 2673838Shsul@eecs.umich.edu lookupTable.erase(i); 2683838Shsul@eecs.umich.edu } 2693838Shsul@eecs.umich.edu 2705004Sgblack@eecs.umich.edu DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn); 2713838Shsul@eecs.umich.edu 2725004Sgblack@eecs.umich.edu table[nlu] = entry; 2733838Shsul@eecs.umich.edu table[nlu].tag = vaddr.vpn(); 2743838Shsul@eecs.umich.edu table[nlu].valid = true; 2753838Shsul@eecs.umich.edu 2763838Shsul@eecs.umich.edu lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 2773838Shsul@eecs.umich.edu nextnlu(); 2783838Shsul@eecs.umich.edu} 2793838Shsul@eecs.umich.edu 2803838Shsul@eecs.umich.eduvoid 2813838Shsul@eecs.umich.eduTLB::flushAll() 2823838Shsul@eecs.umich.edu{ 2833838Shsul@eecs.umich.edu DPRINTF(TLB, "flushAll\n"); 28410905Sandreas.sandberg@arm.com std::fill(table.begin(), table.end(), TlbEntry()); 2854957Sacolyte@umich.edu flushCache(); 2863838Shsul@eecs.umich.edu lookupTable.clear(); 2873838Shsul@eecs.umich.edu nlu = 0; 2883838Shsul@eecs.umich.edu} 2893838Shsul@eecs.umich.edu 2903838Shsul@eecs.umich.eduvoid 2913838Shsul@eecs.umich.eduTLB::flushProcesses() 2923838Shsul@eecs.umich.edu{ 2934957Sacolyte@umich.edu flushCache(); 2943838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.begin(); 2953838Shsul@eecs.umich.edu PageTable::iterator end = lookupTable.end(); 2963838Shsul@eecs.umich.edu while (i != end) { 2973838Shsul@eecs.umich.edu int index = i->second; 2985004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 2995004Sgblack@eecs.umich.edu assert(entry->valid); 3003838Shsul@eecs.umich.edu 3013838Shsul@eecs.umich.edu // we can't increment i after we erase it, so save a copy and 3023838Shsul@eecs.umich.edu // increment it to get the next entry now 3033838Shsul@eecs.umich.edu PageTable::iterator cur = i; 3043838Shsul@eecs.umich.edu ++i; 3053838Shsul@eecs.umich.edu 3065004Sgblack@eecs.umich.edu if (!entry->asma) { 3075569Snate@binkert.org DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, 3085569Snate@binkert.org entry->tag, entry->ppn); 3095004Sgblack@eecs.umich.edu entry->valid = false; 3103838Shsul@eecs.umich.edu lookupTable.erase(cur); 3113453Sgblack@eecs.umich.edu } 3123453Sgblack@eecs.umich.edu } 3133838Shsul@eecs.umich.edu} 3142SN/A 3153838Shsul@eecs.umich.eduvoid 3163838Shsul@eecs.umich.eduTLB::flushAddr(Addr addr, uint8_t asn) 3173838Shsul@eecs.umich.edu{ 3184957Sacolyte@umich.edu flushCache(); 3193838Shsul@eecs.umich.edu VAddr vaddr = addr; 3202SN/A 3213838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(vaddr.vpn()); 3223838Shsul@eecs.umich.edu if (i == lookupTable.end()) 3233838Shsul@eecs.umich.edu return; 3242SN/A 3254428Ssaidi@eecs.umich.edu while (i != lookupTable.end() && i->first == vaddr.vpn()) { 3263838Shsul@eecs.umich.edu int index = i->second; 3275004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 3285004Sgblack@eecs.umich.edu assert(entry->valid); 3293453Sgblack@eecs.umich.edu 3305004Sgblack@eecs.umich.edu if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) { 3313838Shsul@eecs.umich.edu DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 3325004Sgblack@eecs.umich.edu entry->ppn); 3333453Sgblack@eecs.umich.edu 3343838Shsul@eecs.umich.edu // invalidate this entry 3355004Sgblack@eecs.umich.edu entry->valid = false; 3363838Shsul@eecs.umich.edu 3374428Ssaidi@eecs.umich.edu lookupTable.erase(i++); 3384428Ssaidi@eecs.umich.edu } else { 3394428Ssaidi@eecs.umich.edu ++i; 3403838Shsul@eecs.umich.edu } 3413838Shsul@eecs.umich.edu } 3423838Shsul@eecs.umich.edu} 3433838Shsul@eecs.umich.edu 3443838Shsul@eecs.umich.edu 3453838Shsul@eecs.umich.eduvoid 34610905Sandreas.sandberg@arm.comTLB::serialize(CheckpointOut &cp) const 3473838Shsul@eecs.umich.edu{ 34810905Sandreas.sandberg@arm.com const unsigned size(table.size()); 3493838Shsul@eecs.umich.edu SERIALIZE_SCALAR(size); 3503838Shsul@eecs.umich.edu SERIALIZE_SCALAR(nlu); 3513838Shsul@eecs.umich.edu 35210905Sandreas.sandberg@arm.com for (int i = 0; i < size; i++) 35310905Sandreas.sandberg@arm.com table[i].serializeSection(cp, csprintf("Entry%d", i)); 3543838Shsul@eecs.umich.edu} 3553838Shsul@eecs.umich.edu 3563838Shsul@eecs.umich.eduvoid 35710905Sandreas.sandberg@arm.comTLB::unserialize(CheckpointIn &cp) 3583838Shsul@eecs.umich.edu{ 35910905Sandreas.sandberg@arm.com unsigned size(0); 3603838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(size); 3613838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(nlu); 3623838Shsul@eecs.umich.edu 36310905Sandreas.sandberg@arm.com table.resize(size); 3643838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 36510905Sandreas.sandberg@arm.com table[i].unserializeSection(cp, csprintf("Entry%d", i)); 3663838Shsul@eecs.umich.edu if (table[i].valid) { 3673838Shsul@eecs.umich.edu lookupTable.insert(make_pair(table[i].tag, i)); 3683838Shsul@eecs.umich.edu } 3693838Shsul@eecs.umich.edu } 3703838Shsul@eecs.umich.edu} 3713838Shsul@eecs.umich.edu 3723838Shsul@eecs.umich.eduFault 3736022Sgblack@eecs.umich.eduTLB::translateInst(RequestPtr req, ThreadContext *tc) 3743838Shsul@eecs.umich.edu{ 3754375Sgblack@eecs.umich.edu //If this is a pal pc, then set PHYSICAL 3768738Sgblack@eecs.umich.edu if (FullSystem && PcPAL(req->getPC())) 3775736Snate@binkert.org req->setFlags(Request::PHYSICAL); 3784375Sgblack@eecs.umich.edu 3793838Shsul@eecs.umich.edu if (PcPAL(req->getPC())) { 3803838Shsul@eecs.umich.edu // strip off PAL PC marker (lsb is 1) 3813838Shsul@eecs.umich.edu req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 3826022Sgblack@eecs.umich.edu fetch_hits++; 3833838Shsul@eecs.umich.edu return NoFault; 3843453Sgblack@eecs.umich.edu } 3853453Sgblack@eecs.umich.edu 3865736Snate@binkert.org if (req->getFlags() & Request::PHYSICAL) { 3873838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 3883838Shsul@eecs.umich.edu } else { 3893838Shsul@eecs.umich.edu // verify that this is a good virtual address 3903838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 3916022Sgblack@eecs.umich.edu fetch_acv++; 39210474Sandreas.hansson@arm.com return std::make_shared<ItbAcvFault>(req->getVaddr()); 3932SN/A } 3942SN/A 3953838Shsul@eecs.umich.edu 3963838Shsul@eecs.umich.edu // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 3973838Shsul@eecs.umich.edu // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 3986025Snate@binkert.org if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { 3993838Shsul@eecs.umich.edu // only valid in kernel mode 4004172Ssaidi@eecs.umich.edu if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 4013838Shsul@eecs.umich.edu mode_kernel) { 4026022Sgblack@eecs.umich.edu fetch_acv++; 40310474Sandreas.hansson@arm.com return std::make_shared<ItbAcvFault>(req->getVaddr()); 404555SN/A } 4052SN/A 4063838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 407551SN/A 4083838Shsul@eecs.umich.edu // sign extend the physical address properly 4093838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 4103838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 4113838Shsul@eecs.umich.edu else 4123838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 4133838Shsul@eecs.umich.edu } else { 4143838Shsul@eecs.umich.edu // not a physical address: need to look up pte 4154172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 4165004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), 4173838Shsul@eecs.umich.edu asn); 4183838Shsul@eecs.umich.edu 4195004Sgblack@eecs.umich.edu if (!entry) { 4206022Sgblack@eecs.umich.edu fetch_misses++; 42110474Sandreas.hansson@arm.com return std::make_shared<ItbPageFault>(req->getVaddr()); 4223838Shsul@eecs.umich.edu } 4233838Shsul@eecs.umich.edu 4245004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 4253838Shsul@eecs.umich.edu (VAddr(req->getVaddr()).offset() 4263838Shsul@eecs.umich.edu & ~3)); 4273838Shsul@eecs.umich.edu 4283838Shsul@eecs.umich.edu // check permissions for this access 4295004Sgblack@eecs.umich.edu if (!(entry->xre & 4304172Ssaidi@eecs.umich.edu (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { 4313838Shsul@eecs.umich.edu // instruction access fault 4326022Sgblack@eecs.umich.edu fetch_acv++; 43310474Sandreas.hansson@arm.com return std::make_shared<ItbAcvFault>(req->getVaddr()); 4343838Shsul@eecs.umich.edu } 4353838Shsul@eecs.umich.edu 4366022Sgblack@eecs.umich.edu fetch_hits++; 4373838Shsul@eecs.umich.edu } 4383838Shsul@eecs.umich.edu } 4393838Shsul@eecs.umich.edu 4403838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 4418591Sgblack@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) { 44210474Sandreas.hansson@arm.com return std::make_shared<MachineCheckFault>(); 4438591Sgblack@eecs.umich.edu } 4443838Shsul@eecs.umich.edu 4455532Ssaidi@eecs.umich.edu return checkCacheability(req, true); 4463838Shsul@eecs.umich.edu 4473838Shsul@eecs.umich.edu} 4483838Shsul@eecs.umich.edu 4493838Shsul@eecs.umich.eduFault 4506022Sgblack@eecs.umich.eduTLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 4513838Shsul@eecs.umich.edu{ 4523838Shsul@eecs.umich.edu mode_type mode = 4534172Ssaidi@eecs.umich.edu (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 4543838Shsul@eecs.umich.edu 4553838Shsul@eecs.umich.edu /** 4563838Shsul@eecs.umich.edu * Check for alignment faults 4573838Shsul@eecs.umich.edu */ 4583838Shsul@eecs.umich.edu if (req->getVaddr() & (req->getSize() - 1)) { 4596185Sksewell@umich.edu DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(), 4603838Shsul@eecs.umich.edu req->getSize()); 4613838Shsul@eecs.umich.edu uint64_t flags = write ? MM_STAT_WR_MASK : 0; 46210474Sandreas.hansson@arm.com return std::make_shared<DtbAlignmentFault>(req->getVaddr(), 46310474Sandreas.hansson@arm.com req->getFlags(), 46410474Sandreas.hansson@arm.com flags); 4653838Shsul@eecs.umich.edu } 4663838Shsul@eecs.umich.edu 4678408Sksewell@umich.edu if (PcPAL(req->getPC())) { 46810823SAndreas.Sandberg@ARM.com mode = (req->getFlags() & AlphaRequestFlags::ALTMODE) ? 4693838Shsul@eecs.umich.edu (mode_type)ALT_MODE_AM( 4704172Ssaidi@eecs.umich.edu tc->readMiscRegNoEffect(IPR_ALT_MODE)) 4713838Shsul@eecs.umich.edu : mode_kernel; 4723838Shsul@eecs.umich.edu } 4733838Shsul@eecs.umich.edu 4745736Snate@binkert.org if (req->getFlags() & Request::PHYSICAL) { 4753838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 4763838Shsul@eecs.umich.edu } else { 4773838Shsul@eecs.umich.edu // verify that this is a good virtual address 4783838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 4793838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 4803838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 4813838Shsul@eecs.umich.edu MM_STAT_BAD_VA_MASK | 4823838Shsul@eecs.umich.edu MM_STAT_ACV_MASK; 48310474Sandreas.hansson@arm.com return std::make_shared<DtbPageFault>(req->getVaddr(), 48410474Sandreas.hansson@arm.com req->getFlags(), 48510474Sandreas.hansson@arm.com flags); 4863838Shsul@eecs.umich.edu } 4873838Shsul@eecs.umich.edu 4883838Shsul@eecs.umich.edu // Check for "superpage" mapping 4896025Snate@binkert.org if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { 4903838Shsul@eecs.umich.edu // only valid in kernel mode 4914172Ssaidi@eecs.umich.edu if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 4923838Shsul@eecs.umich.edu mode_kernel) { 4933838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 4943838Shsul@eecs.umich.edu uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 4953838Shsul@eecs.umich.edu MM_STAT_ACV_MASK); 4965569Snate@binkert.org 49710474Sandreas.hansson@arm.com return std::make_shared<DtbAcvFault>(req->getVaddr(), 49810474Sandreas.hansson@arm.com req->getFlags(), 49910474Sandreas.hansson@arm.com flags); 5003838Shsul@eecs.umich.edu } 5013838Shsul@eecs.umich.edu 5023838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 5033838Shsul@eecs.umich.edu 5043838Shsul@eecs.umich.edu // sign extend the physical address properly 5053838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 5063838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 5073838Shsul@eecs.umich.edu else 5083838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 5093838Shsul@eecs.umich.edu } else { 5103838Shsul@eecs.umich.edu if (write) 5113838Shsul@eecs.umich.edu write_accesses++; 5123838Shsul@eecs.umich.edu else 5133838Shsul@eecs.umich.edu read_accesses++; 5143838Shsul@eecs.umich.edu 5154172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 5163838Shsul@eecs.umich.edu 5173838Shsul@eecs.umich.edu // not a physical address: need to look up pte 5185004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn); 5193838Shsul@eecs.umich.edu 5205004Sgblack@eecs.umich.edu if (!entry) { 5213838Shsul@eecs.umich.edu // page fault 5223838Shsul@eecs.umich.edu if (write) { write_misses++; } else { read_misses++; } 5233838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 5243838Shsul@eecs.umich.edu MM_STAT_DTB_MISS_MASK; 52510823SAndreas.Sandberg@ARM.com return (req->getFlags() & AlphaRequestFlags::VPTE) ? 52610474Sandreas.hansson@arm.com (Fault)(std::make_shared<PDtbMissFault>(req->getVaddr(), 52710474Sandreas.hansson@arm.com req->getFlags(), 52810474Sandreas.hansson@arm.com flags)) : 52910474Sandreas.hansson@arm.com (Fault)(std::make_shared<NDtbMissFault>(req->getVaddr(), 53010474Sandreas.hansson@arm.com req->getFlags(), 53110474Sandreas.hansson@arm.com flags)); 5323838Shsul@eecs.umich.edu } 5333838Shsul@eecs.umich.edu 5345004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 5353838Shsul@eecs.umich.edu VAddr(req->getVaddr()).offset()); 5363838Shsul@eecs.umich.edu 5373838Shsul@eecs.umich.edu if (write) { 5385004Sgblack@eecs.umich.edu if (!(entry->xwe & MODE2MASK(mode))) { 5393838Shsul@eecs.umich.edu // declare the instruction access fault 5403838Shsul@eecs.umich.edu write_acv++; 5413838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_WR_MASK | 5423838Shsul@eecs.umich.edu MM_STAT_ACV_MASK | 5435004Sgblack@eecs.umich.edu (entry->fonw ? MM_STAT_FONW_MASK : 0); 54410474Sandreas.hansson@arm.com return std::make_shared<DtbPageFault>(req->getVaddr(), 54510474Sandreas.hansson@arm.com req->getFlags(), 54610474Sandreas.hansson@arm.com flags); 5473838Shsul@eecs.umich.edu } 5485004Sgblack@eecs.umich.edu if (entry->fonw) { 5493838Shsul@eecs.umich.edu write_acv++; 5505569Snate@binkert.org uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK; 55110474Sandreas.hansson@arm.com return std::make_shared<DtbPageFault>(req->getVaddr(), 55210474Sandreas.hansson@arm.com req->getFlags(), 55310474Sandreas.hansson@arm.com flags); 5543838Shsul@eecs.umich.edu } 5553453Sgblack@eecs.umich.edu } else { 5565004Sgblack@eecs.umich.edu if (!(entry->xre & MODE2MASK(mode))) { 5573838Shsul@eecs.umich.edu read_acv++; 5583838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_ACV_MASK | 5595004Sgblack@eecs.umich.edu (entry->fonr ? MM_STAT_FONR_MASK : 0); 56010474Sandreas.hansson@arm.com return std::make_shared<DtbAcvFault>(req->getVaddr(), 56110474Sandreas.hansson@arm.com req->getFlags(), 56210474Sandreas.hansson@arm.com flags); 5633453Sgblack@eecs.umich.edu } 5645004Sgblack@eecs.umich.edu if (entry->fonr) { 5653838Shsul@eecs.umich.edu read_acv++; 5663838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_FONR_MASK; 56710474Sandreas.hansson@arm.com return std::make_shared<DtbPageFault>(req->getVaddr(), 56810474Sandreas.hansson@arm.com req->getFlags(), 56910474Sandreas.hansson@arm.com flags); 5703453Sgblack@eecs.umich.edu } 5712SN/A } 5722SN/A } 573551SN/A 5743838Shsul@eecs.umich.edu if (write) 5753838Shsul@eecs.umich.edu write_hits++; 5763838Shsul@eecs.umich.edu else 5773838Shsul@eecs.umich.edu read_hits++; 5782SN/A } 5792SN/A 5803838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 5818591Sgblack@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) { 58210474Sandreas.hansson@arm.com return std::make_shared<MachineCheckFault>(); 5838591Sgblack@eecs.umich.edu } 584551SN/A 5853838Shsul@eecs.umich.edu return checkCacheability(req); 5863838Shsul@eecs.umich.edu} 5873453Sgblack@eecs.umich.edu 5885004Sgblack@eecs.umich.eduTlbEntry & 5893838Shsul@eecs.umich.eduTLB::index(bool advance) 5903838Shsul@eecs.umich.edu{ 5915004Sgblack@eecs.umich.edu TlbEntry *entry = &table[nlu]; 5923453Sgblack@eecs.umich.edu 5933838Shsul@eecs.umich.edu if (advance) 5943838Shsul@eecs.umich.edu nextnlu(); 5953453Sgblack@eecs.umich.edu 5965004Sgblack@eecs.umich.edu return *entry; 5973838Shsul@eecs.umich.edu} 5983453Sgblack@eecs.umich.edu 5996022Sgblack@eecs.umich.eduFault 6006023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 6016022Sgblack@eecs.umich.edu{ 6026023Snate@binkert.org if (mode == Execute) 6036022Sgblack@eecs.umich.edu return translateInst(req, tc); 6046022Sgblack@eecs.umich.edu else 6056023Snate@binkert.org return translateData(req, tc, mode == Write); 6066022Sgblack@eecs.umich.edu} 6076022Sgblack@eecs.umich.edu 6086022Sgblack@eecs.umich.eduvoid 6096022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 6106023Snate@binkert.org Translation *translation, Mode mode) 6116022Sgblack@eecs.umich.edu{ 6126022Sgblack@eecs.umich.edu assert(translation); 6136023Snate@binkert.org translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 6146022Sgblack@eecs.umich.edu} 6156022Sgblack@eecs.umich.edu 6168888Sgeoffrey.blake@arm.comFault 6178888Sgeoffrey.blake@arm.comTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 6188888Sgeoffrey.blake@arm.com{ 6198888Sgeoffrey.blake@arm.com panic("Not implemented\n"); 6208888Sgeoffrey.blake@arm.com return NoFault; 6218888Sgeoffrey.blake@arm.com} 6228888Sgeoffrey.blake@arm.com 6239738Sandreas@sandberg.pp.seFault 6249738Sandreas@sandberg.pp.seTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 6259738Sandreas@sandberg.pp.se{ 6269738Sandreas@sandberg.pp.se return NoFault; 6279738Sandreas@sandberg.pp.se} 6289738Sandreas@sandberg.pp.se 6297811Ssteve.reinhardt@amd.com} // namespace AlphaISA 6304088Sbinkertn@umich.edu 6316022Sgblack@eecs.umich.eduAlphaISA::TLB * 6326022Sgblack@eecs.umich.eduAlphaTLBParams::create() 6333838Shsul@eecs.umich.edu{ 6346022Sgblack@eecs.umich.edu return new AlphaISA::TLB(this); 6353838Shsul@eecs.umich.edu} 636