registers.hh revision 13611:c8b7847b4171
16691Stjones1@inf.ed.ac.uk/* 26691Stjones1@inf.ed.ac.uk * Copyright (c) 2003-2005 The Regents of The University of Michigan 36691Stjones1@inf.ed.ac.uk * All rights reserved. 46691Stjones1@inf.ed.ac.uk * 56691Stjones1@inf.ed.ac.uk * Redistribution and use in source and binary forms, with or without 66691Stjones1@inf.ed.ac.uk * modification, are permitted provided that the following conditions are 76691Stjones1@inf.ed.ac.uk * met: redistributions of source code must retain the above copyright 86691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer; 96691Stjones1@inf.ed.ac.uk * redistributions in binary form must reproduce the above copyright 106691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer in the 116691Stjones1@inf.ed.ac.uk * documentation and/or other materials provided with the distribution; 126691Stjones1@inf.ed.ac.uk * neither the name of the copyright holders nor the names of its 136691Stjones1@inf.ed.ac.uk * contributors may be used to endorse or promote products derived from 146691Stjones1@inf.ed.ac.uk * this software without specific prior written permission. 156691Stjones1@inf.ed.ac.uk * 166691Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176691Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186691Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196691Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206691Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216691Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226691Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236691Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246691Stjones1@inf.ed.ac.uk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256691Stjones1@inf.ed.ac.uk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266691Stjones1@inf.ed.ac.uk * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276691Stjones1@inf.ed.ac.uk * 286691Stjones1@inf.ed.ac.uk * Authors: Gabe Black 296691Stjones1@inf.ed.ac.uk */ 306691Stjones1@inf.ed.ac.uk 316691Stjones1@inf.ed.ac.uk#ifndef __ARCH_ALPHA_REGISTERS_HH__ 326691Stjones1@inf.ed.ac.uk#define __ARCH_ALPHA_REGISTERS_HH__ 3311793Sbrandon.potter@amd.com 3411793Sbrandon.potter@amd.com#include "arch/alpha/generated/max_inst_regs.hh" 356691Stjones1@inf.ed.ac.uk#include "arch/alpha/ipr.hh" 366691Stjones1@inf.ed.ac.uk#include "arch/generic/types.hh" 376691Stjones1@inf.ed.ac.uk#include "arch/generic/vec_pred_reg.hh" 386691Stjones1@inf.ed.ac.uk#include "arch/generic/vec_reg.hh" 3912334Sgabeblack@google.com#include "base/types.hh" 406691Stjones1@inf.ed.ac.uk 418232Snate@binkert.orgnamespace AlphaISA { 426691Stjones1@inf.ed.ac.uk 4311854Sbrandon.potter@amd.comusing AlphaISAInst::MaxInstSrcRegs; 446691Stjones1@inf.ed.ac.ukusing AlphaISAInst::MaxInstDestRegs; 4511800Sbrandon.potter@amd.com 466691Stjones1@inf.ed.ac.uk// Locked read/write flags are can't be detected by the ISA parser 476691Stjones1@inf.ed.ac.ukconst int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1; 486691Stjones1@inf.ed.ac.uk 496691Stjones1@inf.ed.ac.uktypedef RegVal IntReg; 506691Stjones1@inf.ed.ac.uk 5111851Sbrandon.potter@amd.com// floating point register file entry type 5211851Sbrandon.potter@amd.comtypedef RegVal FloatReg; 536691Stjones1@inf.ed.ac.uk 5411905SBrandon.Potter@amd.com// control register file contents 5511905SBrandon.Potter@amd.comtypedef RegVal MiscReg; 5611905SBrandon.Potter@amd.com 5711905SBrandon.Potter@amd.com// dummy typedef since we don't have CC regs 5811905SBrandon.Potter@amd.comtypedef uint8_t CCReg; 5911905SBrandon.Potter@amd.com 6011905SBrandon.Potter@amd.com// Not applicable to Alpha 6111905SBrandon.Potter@amd.comusing VecElem = ::DummyVecElem; 626691Stjones1@inf.ed.ac.ukusing VecReg = ::DummyVecReg; 636691Stjones1@inf.ed.ac.ukusing ConstVecReg = ::DummyConstVecReg; 6411905SBrandon.Potter@amd.comusing VecRegContainer = ::DummyVecRegContainer; 656691Stjones1@inf.ed.ac.ukconstexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; 666691Stjones1@inf.ed.ac.ukconstexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes; 6711905SBrandon.Potter@amd.com 6811905SBrandon.Potter@amd.com// Not applicable to Alpha 6911905SBrandon.Potter@amd.comusing VecPredReg = ::DummyVecPredReg; 7011905SBrandon.Potter@amd.comusing ConstVecPredReg = ::DummyConstVecPredReg; 716691Stjones1@inf.ed.ac.ukusing VecPredRegContainer = ::DummyVecPredRegContainer; 726691Stjones1@inf.ed.ac.ukconstexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits; 736691Stjones1@inf.ed.ac.ukconstexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr; 7411851Sbrandon.potter@amd.com 756691Stjones1@inf.ed.ac.ukenum MiscRegIndex 767532Ssteve.reinhardt@amd.com{ 777532Ssteve.reinhardt@amd.com MISCREG_FPCR = NumInternalProcRegs, 7810318Sandreas.hansson@arm.com MISCREG_UNIQ, 796691Stjones1@inf.ed.ac.uk MISCREG_LOCKFLAG, 806691Stjones1@inf.ed.ac.uk MISCREG_LOCKADDR, 816691Stjones1@inf.ed.ac.uk MISCREG_INTR, 8211851Sbrandon.potter@amd.com NUM_MISCREGS 836691Stjones1@inf.ed.ac.uk}; 846691Stjones1@inf.ed.ac.uk 856691Stjones1@inf.ed.ac.uk// semantically meaningful register indices 866691Stjones1@inf.ed.ac.ukconst RegIndex ZeroReg = 31; // architecturally meaningful 876691Stjones1@inf.ed.ac.uk// the rest of these depend on the ABI 886691Stjones1@inf.ed.ac.ukconst RegIndex StackPointerReg = 30; 896691Stjones1@inf.ed.ac.ukconst RegIndex GlobalPointerReg = 29; 906691Stjones1@inf.ed.ac.ukconst RegIndex ProcedureValueReg = 27; 916691Stjones1@inf.ed.ac.ukconst RegIndex ReturnAddressReg = 26; 926691Stjones1@inf.ed.ac.ukconst RegIndex ReturnValueReg = 0; 936691Stjones1@inf.ed.ac.ukconst RegIndex FramePointerReg = 15; 946691Stjones1@inf.ed.ac.uk 956691Stjones1@inf.ed.ac.ukconst RegIndex SyscallNumReg = 0; 9611389Sbrandon.potter@amd.comconst RegIndex FirstArgumentReg = 16; 9711389Sbrandon.potter@amd.comconst RegIndex SyscallPseudoReturnReg = 20; 9811389Sbrandon.potter@amd.comconst RegIndex SyscallSuccessReg = 19; 996691Stjones1@inf.ed.ac.uk 1006691Stjones1@inf.ed.ac.ukconst int NumIntArchRegs = 32; 1016691Stjones1@inf.ed.ac.ukconst int NumPALShadowRegs = 8; 1026691Stjones1@inf.ed.ac.ukconst int NumFloatArchRegs = 32; 1036691Stjones1@inf.ed.ac.uk 1046691Stjones1@inf.ed.ac.ukconst int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 1056691Stjones1@inf.ed.ac.ukconst int NumFloatRegs = NumFloatArchRegs; 1066691Stjones1@inf.ed.ac.ukconst int NumVecRegs = 1; // Not applicable to Alpha 1076691Stjones1@inf.ed.ac.uk // (1 to prevent warnings) 1086691Stjones1@inf.ed.ac.ukconst int NumVecPredRegs = 1; // Not applicable to Alpha 1096691Stjones1@inf.ed.ac.uk // (1 to prevent warnings) 1106691Stjones1@inf.ed.ac.ukconst int NumCCRegs = 0; 1116691Stjones1@inf.ed.ac.ukconst int NumMiscRegs = NUM_MISCREGS; 11210318Sandreas.hansson@arm.com 1136691Stjones1@inf.ed.ac.ukconst int TotalNumRegs = 1146691Stjones1@inf.ed.ac.uk NumIntRegs + NumFloatRegs + NumMiscRegs; 1156691Stjones1@inf.ed.ac.uk 1166691Stjones1@inf.ed.ac.uk} // namespace AlphaISA 1176691Stjones1@inf.ed.ac.uk 1186691Stjones1@inf.ed.ac.uk#endif // __ARCH_ALPHA_REGFILE_HH__ 1196691Stjones1@inf.ed.ac.uk