registers.hh revision 10934:5af8f40d8f2c
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_ALPHA_REGISTERS_HH__ 32#define __ARCH_ALPHA_REGISTERS_HH__ 33 34#include "arch/alpha/generated/max_inst_regs.hh" 35#include "arch/alpha/ipr.hh" 36#include "base/types.hh" 37 38namespace AlphaISA { 39 40using AlphaISAInst::MaxInstSrcRegs; 41using AlphaISAInst::MaxInstDestRegs; 42 43// Locked read/write flags are can't be detected by the ISA parser 44const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1; 45 46typedef uint8_t RegIndex; 47typedef uint64_t IntReg; 48 49// floating point register file entry type 50typedef double FloatReg; 51typedef uint64_t FloatRegBits; 52 53// control register file contents 54typedef uint64_t MiscReg; 55 56// dummy typedef since we don't have CC regs 57typedef uint8_t CCReg; 58 59// vector register file entry type 60typedef uint64_t VectorRegElement; 61const int NumVectorRegElements = 0; 62const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement); 63typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg; 64 65union AnyReg 66{ 67 IntReg intreg; 68 FloatReg fpreg; 69 MiscReg ctrlreg; 70}; 71 72enum MiscRegIndex 73{ 74 MISCREG_FPCR = NumInternalProcRegs, 75 MISCREG_UNIQ, 76 MISCREG_LOCKFLAG, 77 MISCREG_LOCKADDR, 78 MISCREG_INTR, 79 NUM_MISCREGS 80}; 81 82// semantically meaningful register indices 83const RegIndex ZeroReg = 31; // architecturally meaningful 84// the rest of these depend on the ABI 85const RegIndex StackPointerReg = 30; 86const RegIndex GlobalPointerReg = 29; 87const RegIndex ProcedureValueReg = 27; 88const RegIndex ReturnAddressReg = 26; 89const RegIndex ReturnValueReg = 0; 90const RegIndex FramePointerReg = 15; 91 92const RegIndex SyscallNumReg = 0; 93const RegIndex FirstArgumentReg = 16; 94const RegIndex SyscallPseudoReturnReg = 20; 95const RegIndex SyscallSuccessReg = 19; 96 97const int NumIntArchRegs = 32; 98const int NumPALShadowRegs = 8; 99const int NumFloatArchRegs = 32; 100 101const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 102const int NumFloatRegs = NumFloatArchRegs; 103const int NumCCRegs = 0; 104const int NumVectorRegs = 0; 105const int NumMiscRegs = NUM_MISCREGS; 106 107const int TotalNumRegs = 108 NumIntRegs + NumFloatRegs + NumMiscRegs; 109 110// These enumerate all the registers for dependence tracking. 111enum DependenceTags { 112 // 0..31 are the integer regs 0..31 113 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base) 114 FP_Reg_Base = NumIntRegs, 115 CC_Reg_Base = FP_Reg_Base + NumFloatRegs, 116 Vector_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0 117 Misc_Reg_Base = Vector_Reg_Base + NumCCRegs, // NumVectorRegs == 0 118 Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs 119}; 120 121} // namespace AlphaISA 122 123#endif // __ARCH_ALPHA_REGFILE_HH__ 124