registers.hh revision 9046
16184SN/A/* 26184SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 36184SN/A * All rights reserved. 46184SN/A * 56184SN/A * Redistribution and use in source and binary forms, with or without 66184SN/A * modification, are permitted provided that the following conditions are 76184SN/A * met: redistributions of source code must retain the above copyright 86184SN/A * notice, this list of conditions and the following disclaimer; 96184SN/A * redistributions in binary form must reproduce the above copyright 106184SN/A * notice, this list of conditions and the following disclaimer in the 116184SN/A * documentation and/or other materials provided with the distribution; 126184SN/A * neither the name of the copyright holders nor the names of its 136184SN/A * contributors may be used to endorse or promote products derived from 146184SN/A * this software without specific prior written permission. 156184SN/A * 166184SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176184SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186184SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196184SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206184SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216184SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226184SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236184SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246184SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256184SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266184SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276184SN/A * 286184SN/A * Authors: Gabe Black 296184SN/A */ 306184SN/A 3111793Sbrandon.potter@amd.com#ifndef __ARCH_ALPHA_REGISTERS_HH__ 3211793Sbrandon.potter@amd.com#define __ARCH_ALPHA_REGISTERS_HH__ 336184SN/A 3412334Sgabeblack@google.com#include "arch/alpha/generated/max_inst_regs.hh" 356184SN/A#include "arch/alpha/ipr.hh" 368232Snate@binkert.org#include "base/types.hh" 376184SN/A 3810785Sgope@wisc.edunamespace AlphaISA { 399480Snilay@cs.wisc.edu 409480Snilay@cs.wisc.eduusing AlphaISAInst::MaxInstSrcRegs; 4110785Sgope@wisc.eduusing AlphaISAInst::MaxInstDestRegs; 426184SN/A 436184SN/A// Locked read/write flags are can't be detected by the ISA parser 446184SN/Aconst int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1; 456184SN/A 466184SN/Atypedef uint8_t RegIndex; 476184SN/Atypedef uint64_t IntReg; 486184SN/A 496184SN/A// floating point register file entry type 506184SN/Atypedef double FloatReg; 516184SN/Atypedef uint64_t FloatRegBits; 526184SN/A 536184SN/A// control register file contents 546184SN/Atypedef uint64_t MiscReg; 556184SN/A 569480Snilay@cs.wisc.eduunion AnyReg 576184SN/A{ 586184SN/A IntReg intreg; 596184SN/A FloatReg fpreg; 606184SN/A MiscReg ctrlreg; 616227Snate@binkert.org}; 629480Snilay@cs.wisc.edu 636184SN/Aenum MiscRegIndex 649480Snilay@cs.wisc.edu{ 656184SN/A MISCREG_FPCR = NumInternalProcRegs, 666184SN/A MISCREG_UNIQ, 679480Snilay@cs.wisc.edu MISCREG_LOCKFLAG, 686184SN/A MISCREG_LOCKADDR, 699480Snilay@cs.wisc.edu MISCREG_INTR, 706184SN/A NUM_MISCREGS 716184SN/A}; 726184SN/A 736184SN/A// semantically meaningful register indices 746184SN/Aconst RegIndex ZeroReg = 31; // architecturally meaningful 756184SN/A// the rest of these depend on the ABI 766227Snate@binkert.orgconst RegIndex StackPointerReg = 30; 776184SN/Aconst RegIndex GlobalPointerReg = 29; 786184SN/Aconst RegIndex ProcedureValueReg = 27; 796184SN/Aconst RegIndex ReturnAddressReg = 26; 806184SN/Aconst RegIndex ReturnValueReg = 0; 818842Smrinmoy.ghosh@arm.comconst RegIndex FramePointerReg = 15; 8211434Smitch.hayenga@arm.com 838842Smrinmoy.ghosh@arm.comconst RegIndex SyscallNumReg = 0; 848842Smrinmoy.ghosh@arm.comconst RegIndex FirstArgumentReg = 16; 858842Smrinmoy.ghosh@arm.comconst RegIndex SyscallPseudoReturnReg = 20; 868842Smrinmoy.ghosh@arm.comconst RegIndex SyscallSuccessReg = 19; 878842Smrinmoy.ghosh@arm.com 888842Smrinmoy.ghosh@arm.comconst int NumIntArchRegs = 32; 896184SN/Aconst int NumPALShadowRegs = 8; 9011434Smitch.hayenga@arm.comconst int NumFloatArchRegs = 32; 916184SN/Aconst int NumMiscArchRegs = NUM_MISCREGS; 926184SN/A 936184SN/Aconst int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 946184SN/Aconst int NumFloatRegs = NumFloatArchRegs; 956184SN/Aconst int NumMiscRegs = NumMiscArchRegs; 969480Snilay@cs.wisc.edu 976184SN/Aconst int TotalNumRegs = 986184SN/A NumIntRegs + NumFloatRegs + NumMiscRegs; 996184SN/A 1006184SN/Aconst int TotalDataRegs = NumIntRegs + NumFloatRegs; 1019480Snilay@cs.wisc.edu 1026184SN/A// These enumerate all the registers for dependence tracking. 1036184SN/Aenum DependenceTags { 1046184SN/A // 0..31 are the integer regs 0..31 1056184SN/A // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 1066184SN/A FP_Base_DepTag = 40, 1076184SN/A Ctrl_Base_DepTag = 72, 1086184SN/A Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs + NumInternalProcRegs 1099480Snilay@cs.wisc.edu}; 1106184SN/A 1116184SN/A} // namespace AlphaISA 1129480Snilay@cs.wisc.edu 1136184SN/A#endif // __ARCH_ALPHA_REGFILE_HH__ 1146184SN/A