registers.hh revision 13610
12440SN/A/* 22440SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32440SN/A * All rights reserved. 42440SN/A * 52440SN/A * Redistribution and use in source and binary forms, with or without 62440SN/A * modification, are permitted provided that the following conditions are 72440SN/A * met: redistributions of source code must retain the above copyright 82440SN/A * notice, this list of conditions and the following disclaimer; 92440SN/A * redistributions in binary form must reproduce the above copyright 102440SN/A * notice, this list of conditions and the following disclaimer in the 112440SN/A * documentation and/or other materials provided with the distribution; 122440SN/A * neither the name of the copyright holders nor the names of its 132440SN/A * contributors may be used to endorse or promote products derived from 142440SN/A * this software without specific prior written permission. 152440SN/A * 162440SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172440SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182440SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192440SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202440SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212440SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222440SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232440SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242440SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252440SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262440SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Gabe Black 292440SN/A */ 302440SN/A 316329Sgblack@eecs.umich.edu#ifndef __ARCH_ALPHA_REGISTERS_HH__ 326329Sgblack@eecs.umich.edu#define __ARCH_ALPHA_REGISTERS_HH__ 332440SN/A 348961Sgblack@eecs.umich.edu#include "arch/alpha/generated/max_inst_regs.hh" 356327SN/A#include "arch/alpha/ipr.hh" 3612104Snathanael.premillieu@arm.com#include "arch/generic/types.hh" 3713610Sgiacomo.gabrielli@arm.com#include "arch/generic/vec_pred_reg.hh" 3812109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/vec_reg.hh" 396329Sgblack@eecs.umich.edu#include "base/types.hh" 402440SN/A 415569SN/Anamespace AlphaISA { 422972SN/A 436329Sgblack@eecs.umich.eduusing AlphaISAInst::MaxInstSrcRegs; 446329Sgblack@eecs.umich.eduusing AlphaISAInst::MaxInstDestRegs; 456327SN/A 469046SAli.Saidi@ARM.com// Locked read/write flags are can't be detected by the ISA parser 479046SAli.Saidi@ARM.comconst int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1; 489046SAli.Saidi@ARM.com 4913556Sgabeblack@google.comtypedef RegVal IntReg; 506327SN/A 516329Sgblack@eecs.umich.edu// floating point register file entry type 5213556Sgabeblack@google.comtypedef RegVal FloatRegBits; 536327SN/A 546329Sgblack@eecs.umich.edu// control register file contents 5513556Sgabeblack@google.comtypedef RegVal MiscReg; 566327SN/A 579920Syasuko.eckert@amd.com// dummy typedef since we don't have CC regs 589920Syasuko.eckert@amd.comtypedef uint8_t CCReg; 599920Syasuko.eckert@amd.com 6013610Sgiacomo.gabrielli@arm.com// Not applicable to Alpha 6113610Sgiacomo.gabrielli@arm.comusing VecElem = ::DummyVecElem; 6213610Sgiacomo.gabrielli@arm.comusing VecReg = ::DummyVecReg; 6313610Sgiacomo.gabrielli@arm.comusing ConstVecReg = ::DummyConstVecReg; 6413610Sgiacomo.gabrielli@arm.comusing VecRegContainer = ::DummyVecRegContainer; 6513610Sgiacomo.gabrielli@arm.comconstexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; 6613610Sgiacomo.gabrielli@arm.comconstexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes; 6713610Sgiacomo.gabrielli@arm.com 6813610Sgiacomo.gabrielli@arm.com// Not applicable to Alpha 6913610Sgiacomo.gabrielli@arm.comusing VecPredReg = ::DummyVecPredReg; 7013610Sgiacomo.gabrielli@arm.comusing ConstVecPredReg = ::DummyConstVecPredReg; 7113610Sgiacomo.gabrielli@arm.comusing VecPredRegContainer = ::DummyVecPredRegContainer; 7213610Sgiacomo.gabrielli@arm.comconstexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits; 7313610Sgiacomo.gabrielli@arm.comconstexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr; 7412109SRekai.GonzalezAlberquilla@arm.com 756329Sgblack@eecs.umich.eduenum MiscRegIndex 766329Sgblack@eecs.umich.edu{ 776329Sgblack@eecs.umich.edu MISCREG_FPCR = NumInternalProcRegs, 786329Sgblack@eecs.umich.edu MISCREG_UNIQ, 796329Sgblack@eecs.umich.edu MISCREG_LOCKFLAG, 806329Sgblack@eecs.umich.edu MISCREG_LOCKADDR, 817699Sgblack@eecs.umich.edu MISCREG_INTR, 827699Sgblack@eecs.umich.edu NUM_MISCREGS 836329Sgblack@eecs.umich.edu}; 845569SN/A 856329Sgblack@eecs.umich.edu// semantically meaningful register indices 866329Sgblack@eecs.umich.educonst RegIndex ZeroReg = 31; // architecturally meaningful 876329Sgblack@eecs.umich.edu// the rest of these depend on the ABI 886329Sgblack@eecs.umich.educonst RegIndex StackPointerReg = 30; 896329Sgblack@eecs.umich.educonst RegIndex GlobalPointerReg = 29; 906329Sgblack@eecs.umich.educonst RegIndex ProcedureValueReg = 27; 916329Sgblack@eecs.umich.educonst RegIndex ReturnAddressReg = 26; 926329Sgblack@eecs.umich.educonst RegIndex ReturnValueReg = 0; 936329Sgblack@eecs.umich.educonst RegIndex FramePointerReg = 15; 946329Sgblack@eecs.umich.edu 956329Sgblack@eecs.umich.educonst RegIndex SyscallNumReg = 0; 966329Sgblack@eecs.umich.educonst RegIndex FirstArgumentReg = 16; 976329Sgblack@eecs.umich.educonst RegIndex SyscallPseudoReturnReg = 20; 986329Sgblack@eecs.umich.educonst RegIndex SyscallSuccessReg = 19; 996329Sgblack@eecs.umich.edu 1006329Sgblack@eecs.umich.educonst int NumIntArchRegs = 32; 1016329Sgblack@eecs.umich.educonst int NumPALShadowRegs = 8; 1026329Sgblack@eecs.umich.educonst int NumFloatArchRegs = 32; 1036329Sgblack@eecs.umich.edu 1046329Sgblack@eecs.umich.educonst int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 1056329Sgblack@eecs.umich.educonst int NumFloatRegs = NumFloatArchRegs; 10613610Sgiacomo.gabrielli@arm.comconst int NumVecRegs = 1; // Not applicable to Alpha 10713610Sgiacomo.gabrielli@arm.com // (1 to prevent warnings) 10813610Sgiacomo.gabrielli@arm.comconst int NumVecPredRegs = 1; // Not applicable to Alpha 10913610Sgiacomo.gabrielli@arm.com // (1 to prevent warnings) 1109920Syasuko.eckert@amd.comconst int NumCCRegs = 0; 1119917Ssteve.reinhardt@amd.comconst int NumMiscRegs = NUM_MISCREGS; 1126329Sgblack@eecs.umich.edu 1136329Sgblack@eecs.umich.educonst int TotalNumRegs = 1147699Sgblack@eecs.umich.edu NumIntRegs + NumFloatRegs + NumMiscRegs; 1156329Sgblack@eecs.umich.edu 1162440SN/A} // namespace AlphaISA 1172440SN/A 1185569SN/A#endif // __ARCH_ALPHA_REGFILE_HH__ 119