process.cc revision 4997:e7380529bd2d
12SN/A/*
210298Salexandru.dutu@amd.com * Copyright (c) 2003-2004 The Regents of The University of Michigan
31762SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272SN/A *
282665Ssaidi@eecs.umich.edu * Authors: Gabe Black
292665Ssaidi@eecs.umich.edu *          Ali Saidi
302665Ssaidi@eecs.umich.edu */
312SN/A
322SN/A#include "arch/alpha/isa_traits.hh"
33360SN/A#include "arch/alpha/process.hh"
34360SN/A#include "base/loader/object_file.hh"
352SN/A#include "base/misc.hh"
3611854Sbrandon.potter@amd.com#include "cpu/thread_context.hh"
3711854Sbrandon.potter@amd.com#include "sim/system.hh"
3810930Sbrandon.potter@amd.com
3911800Sbrandon.potter@amd.com
404117Sgblack@eecs.umich.eduusing namespace AlphaISA;
41180SN/Ausing namespace std;
422SN/A
436329Sgblack@eecs.umich.eduAlphaLiveProcess::AlphaLiveProcess(const std::string &nm, ObjectFile *objFile,
442378SN/A        System *_system, int stdin_fd, int stdout_fd, int stderr_fd,
456214Snate@binkert.org        std::vector<std::string> &argv, std::vector<std::string> &envp,
466658Snate@binkert.org        const std::string &cwd,
478852Sandreas.hansson@arm.com        uint64_t _uid, uint64_t _euid, uint64_t _gid, uint64_t _egid,
4810930Sbrandon.potter@amd.com        uint64_t _pid, uint64_t _ppid)
4956SN/A    : LiveProcess(nm, objFile, _system, stdin_fd, stdout_fd, stderr_fd,
502SN/A        argv, envp, cwd, _uid, _euid, _gid, _egid, _pid, _ppid)
518737Skoansin.tan@gmail.com{
5211800Sbrandon.potter@amd.com    brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
5311800Sbrandon.potter@amd.com    brk_point = roundUp(brk_point, VMPageSize);
5411851Sbrandon.potter@amd.com
5511800Sbrandon.potter@amd.com    // Set up stack.  On Alpha, stack goes below text section.  This
565154Sgblack@eecs.umich.edu    // code should get moved to some architecture-specific spot.
5711800Sbrandon.potter@amd.com    stack_base = objFile->textBase() - (409600+4096);
585154Sgblack@eecs.umich.edu
592680Sktlim@umich.edu    // Set up region for mmaps.  Tru64 seems to start just above 0 and
602378SN/A    // grow up from there.
612SN/A    mmap_start = mmap_end = 0x10000;
622SN/A
632SN/A    // Set pointer for next thread stack.  Reserve 8M for main stack.
642SN/A    next_thread_stack_base = stack_base - (8 * 1024 * 1024);
652SN/A
662SN/A}
672680Sktlim@umich.edu
682SN/Avoid
692680Sktlim@umich.eduAlphaLiveProcess::startup()
702SN/A{
7111854Sbrandon.potter@amd.com    argsInit(MachineBytes, VMPageSize);
722SN/A
732SN/A    threadContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer());
7411854Sbrandon.potter@amd.com    //Opperate in user mode
752SN/A    threadContexts[0]->setMiscRegNoEffect(IPR_ICM, 0x18);
7611854Sbrandon.potter@amd.com    //No super page mapping
7711854Sbrandon.potter@amd.com    threadContexts[0]->setMiscRegNoEffect(IPR_MCSR, 0);
782SN/A    //Set this to 0 for now, but it should be unique for each process
7911169Sandreas.hansson@arm.com    threadContexts[0]->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
8011168Sandreas.hansson@arm.com}
8110905Sandreas.sandberg@arm.com
8211854Sbrandon.potter@amd.com
8311854Sbrandon.potter@amd.com