process.cc revision 11851:824055fe6b30 
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Ali Saidi
30 */
31
32#include "arch/alpha/process.hh"
33
34#include "arch/alpha/isa_traits.hh"
35#include "base/loader/elf_object.hh"
36#include "base/loader/object_file.hh"
37#include "base/misc.hh"
38#include "cpu/thread_context.hh"
39#include "debug/Loader.hh"
40#include "mem/page_table.hh"
41#include "sim/byteswap.hh"
42#include "sim/process_impl.hh"
43#include "sim/syscall_return.hh"
44#include "sim/system.hh"
45
46using namespace AlphaISA;
47using namespace std;
48
49AlphaProcess::AlphaProcess(ProcessParams *params, ObjectFile *objFile)
50    : Process(params, objFile)
51{
52    brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
53    brk_point = roundUp(brk_point, PageBytes);
54
55    // Set up stack.  On Alpha, stack goes below text section.  This
56    // code should get moved to some architecture-specific spot.
57    stack_base = objFile->textBase() - (409600+4096);
58
59    // Set up region for mmaps.  Tru64 seems to start just above 0 and
60    // grow up from there.
61    mmap_end = 0x10000;
62
63    // Set pointer for next thread stack.  Reserve 8M for main stack.
64    next_thread_stack_base = stack_base - (8 * 1024 * 1024);
65
66}
67
68void
69AlphaProcess::argsInit(int intSize, int pageSize)
70{
71    // Patch the ld_bias for dynamic executables.
72    updateBias();
73
74    objFile->loadSections(initVirtMem);
75
76    typedef AuxVector<uint64_t> auxv_t;
77    std::vector<auxv_t>  auxv;
78
79    ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
80    if (elfObject)
81    {
82        // modern glibc uses a bunch of auxiliary vectors to set up
83        // TLS as well as do a bunch of other stuff
84        // these vectors go on the bottom of the stack, below argc/argv/envp
85        // pointers but above actual arg strings
86        // I don't have all the ones glibc looks at here, but so far it doesn't
87        // seem to be a problem.
88        // check out _dl_aux_init() in glibc/elf/dl-support.c for details
89        // --Lisa
90        auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::PageBytes));
91        auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
92        auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
93        DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable());
94        auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
95        // This is the base address of the ELF interpreter; it should be
96        // zero for static executables or contain the base address for
97        // dynamic executables.
98        auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
99        auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
100        auxv.push_back(auxv_t(M5_AT_UID, uid()));
101        auxv.push_back(auxv_t(M5_AT_EUID, euid()));
102        auxv.push_back(auxv_t(M5_AT_GID, gid()));
103        auxv.push_back(auxv_t(M5_AT_EGID, egid()));
104
105    }
106
107    // Calculate how much space we need for arg & env & auxv arrays.
108    int argv_array_size = intSize * (argv.size() + 1);
109    int envp_array_size = intSize * (envp.size() + 1);
110    int auxv_array_size = intSize * 2 * (auxv.size() + 1);
111
112    int arg_data_size = 0;
113    for (vector<string>::size_type i = 0; i < argv.size(); ++i) {
114        arg_data_size += argv[i].size() + 1;
115    }
116    int env_data_size = 0;
117    for (vector<string>::size_type i = 0; i < envp.size(); ++i) {
118        env_data_size += envp[i].size() + 1;
119    }
120
121    int space_needed =
122        argv_array_size +
123        envp_array_size +
124        auxv_array_size +
125        arg_data_size +
126        env_data_size;
127
128    if (space_needed < 32*1024)
129        space_needed = 32*1024;
130
131    // set bottom of stack
132    stack_min = stack_base - space_needed;
133    // align it
134    stack_min = roundDown(stack_min, pageSize);
135    stack_size = stack_base - stack_min;
136    // map memory
137    allocateMem(stack_min, roundUp(stack_size, pageSize));
138
139    // map out initial stack contents
140    Addr argv_array_base = stack_min + intSize; // room for argc
141    Addr envp_array_base = argv_array_base + argv_array_size;
142    Addr auxv_array_base = envp_array_base + envp_array_size;
143    Addr arg_data_base = auxv_array_base + auxv_array_size;
144    Addr env_data_base = arg_data_base + arg_data_size;
145
146    // write contents to stack
147    uint64_t argc = argv.size();
148    if (intSize == 8)
149        argc = htog((uint64_t)argc);
150    else if (intSize == 4)
151        argc = htog((uint32_t)argc);
152    else
153        panic("Unknown int size");
154
155    initVirtMem.writeBlob(stack_min, (uint8_t*)&argc, intSize);
156
157    copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
158    copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
159
160    //Copy the aux stuff
161    for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
162        initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
163                (uint8_t*)&(auxv[x].a_type), intSize);
164        initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
165                (uint8_t*)&(auxv[x].a_val), intSize);
166    }
167
168    ThreadContext *tc = system->getThreadContext(contextIds[0]);
169
170    setSyscallArg(tc, 0, argc);
171    setSyscallArg(tc, 1, argv_array_base);
172    tc->setIntReg(StackPointerReg, stack_min);
173
174    tc->pcState(getStartPC());
175}
176
177void
178AlphaProcess::setupASNReg()
179{
180    ThreadContext *tc = system->getThreadContext(contextIds[0]);
181    tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57);
182}
183
184
185void
186AlphaProcess::loadState(CheckpointIn &cp)
187{
188    Process::loadState(cp);
189    // need to set up ASN after unserialization since _pid value may
190    // come from checkpoint
191    setupASNReg();
192}
193
194
195void
196AlphaProcess::initState()
197{
198    // need to set up ASN before further initialization since init
199    // will involve writing to virtual memory addresses
200    setupASNReg();
201
202    Process::initState();
203
204    argsInit(MachineBytes, PageBytes);
205
206    ThreadContext *tc = system->getThreadContext(contextIds[0]);
207    tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
208    //Operate in user mode
209    tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3);
210    tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3);
211    //No super page mapping
212    tc->setMiscRegNoEffect(IPR_MCSR, 0);
213}
214
215AlphaISA::IntReg
216AlphaProcess::getSyscallArg(ThreadContext *tc, int &i)
217{
218    assert(i < 6);
219    return tc->readIntReg(FirstArgumentReg + i++);
220}
221
222void
223AlphaProcess::setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val)
224{
225    assert(i < 6);
226    tc->setIntReg(FirstArgumentReg + i, val);
227}
228
229void
230AlphaProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
231{
232    // check for error condition.  Alpha syscall convention is to
233    // indicate success/failure in reg a3 (r19) and put the
234    // return value itself in the standard return value reg (v0).
235    if (sysret.successful()) {
236        // no error
237        tc->setIntReg(SyscallSuccessReg, 0);
238        tc->setIntReg(ReturnValueReg, sysret.returnValue());
239    } else {
240        // got an error, return details
241        tc->setIntReg(SyscallSuccessReg, (IntReg)-1);
242        tc->setIntReg(ReturnValueReg, sysret.errnoValue());
243    }
244}
245