process.cc revision 11386:94c09b607a84 
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Ali Saidi
30 */
31
32#include "arch/alpha/isa_traits.hh"
33#include "arch/alpha/process.hh"
34#include "base/loader/elf_object.hh"
35#include "base/loader/object_file.hh"
36#include "base/misc.hh"
37#include "cpu/thread_context.hh"
38#include "debug/Loader.hh"
39#include "mem/page_table.hh"
40#include "sim/byteswap.hh"
41#include "sim/process_impl.hh"
42#include "sim/system.hh"
43
44using namespace AlphaISA;
45using namespace std;
46
47AlphaLiveProcess::AlphaLiveProcess(LiveProcessParams *params,
48                                   ObjectFile *objFile)
49    : LiveProcess(params, objFile)
50{
51    brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
52    brk_point = roundUp(brk_point, PageBytes);
53
54    // Set up stack.  On Alpha, stack goes below text section.  This
55    // code should get moved to some architecture-specific spot.
56    stack_base = objFile->textBase() - (409600+4096);
57
58    // Set up region for mmaps.  Tru64 seems to start just above 0 and
59    // grow up from there.
60    mmap_end = 0x10000;
61
62    // Set pointer for next thread stack.  Reserve 8M for main stack.
63    next_thread_stack_base = stack_base - (8 * 1024 * 1024);
64
65}
66
67void
68AlphaLiveProcess::argsInit(int intSize, int pageSize)
69{
70    objFile->loadSections(initVirtMem);
71
72    typedef AuxVector<uint64_t> auxv_t;
73    std::vector<auxv_t>  auxv;
74
75    ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
76    if (elfObject)
77    {
78        // modern glibc uses a bunch of auxiliary vectors to set up
79        // TLS as well as do a bunch of other stuff
80        // these vectors go on the bottom of the stack, below argc/argv/envp
81        // pointers but above actual arg strings
82        // I don't have all the ones glibc looks at here, but so far it doesn't
83        // seem to be a problem.
84        // check out _dl_aux_init() in glibc/elf/dl-support.c for details
85        // --Lisa
86        auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::PageBytes));
87        auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
88        auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
89        DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable());
90        auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
91        auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
92        auxv.push_back(auxv_t(M5_AT_UID, uid()));
93        auxv.push_back(auxv_t(M5_AT_EUID, euid()));
94        auxv.push_back(auxv_t(M5_AT_GID, gid()));
95        auxv.push_back(auxv_t(M5_AT_EGID, egid()));
96
97    }
98
99    // Calculate how much space we need for arg & env & auxv arrays.
100    int argv_array_size = intSize * (argv.size() + 1);
101    int envp_array_size = intSize * (envp.size() + 1);
102    int auxv_array_size = intSize * 2 * (auxv.size() + 1);
103
104    int arg_data_size = 0;
105    for (vector<string>::size_type i = 0; i < argv.size(); ++i) {
106        arg_data_size += argv[i].size() + 1;
107    }
108    int env_data_size = 0;
109    for (vector<string>::size_type i = 0; i < envp.size(); ++i) {
110        env_data_size += envp[i].size() + 1;
111    }
112
113    int space_needed =
114        argv_array_size +
115        envp_array_size +
116        auxv_array_size +
117        arg_data_size +
118        env_data_size;
119
120    if (space_needed < 32*1024)
121        space_needed = 32*1024;
122
123    // set bottom of stack
124    stack_min = stack_base - space_needed;
125    // align it
126    stack_min = roundDown(stack_min, pageSize);
127    stack_size = stack_base - stack_min;
128    // map memory
129    allocateMem(stack_min, roundUp(stack_size, pageSize));
130
131    // map out initial stack contents
132    Addr argv_array_base = stack_min + intSize; // room for argc
133    Addr envp_array_base = argv_array_base + argv_array_size;
134    Addr auxv_array_base = envp_array_base + envp_array_size;
135    Addr arg_data_base = auxv_array_base + auxv_array_size;
136    Addr env_data_base = arg_data_base + arg_data_size;
137
138    // write contents to stack
139    uint64_t argc = argv.size();
140    if (intSize == 8)
141        argc = htog((uint64_t)argc);
142    else if (intSize == 4)
143        argc = htog((uint32_t)argc);
144    else
145        panic("Unknown int size");
146
147    initVirtMem.writeBlob(stack_min, (uint8_t*)&argc, intSize);
148
149    copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
150    copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
151
152    //Copy the aux stuff
153    for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
154        initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
155                (uint8_t*)&(auxv[x].a_type), intSize);
156        initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
157                (uint8_t*)&(auxv[x].a_val), intSize);
158    }
159
160    ThreadContext *tc = system->getThreadContext(contextIds[0]);
161
162    setSyscallArg(tc, 0, argc);
163    setSyscallArg(tc, 1, argv_array_base);
164    tc->setIntReg(StackPointerReg, stack_min);
165
166    tc->pcState(objFile->entryPoint());
167}
168
169void
170AlphaLiveProcess::setupASNReg()
171{
172    ThreadContext *tc = system->getThreadContext(contextIds[0]);
173    tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
174}
175
176
177void
178AlphaLiveProcess::loadState(CheckpointIn &cp)
179{
180    LiveProcess::loadState(cp);
181    // need to set up ASN after unserialization since M5_pid value may
182    // come from checkpoint
183    setupASNReg();
184}
185
186
187void
188AlphaLiveProcess::initState()
189{
190    // need to set up ASN before further initialization since init
191    // will involve writing to virtual memory addresses
192    setupASNReg();
193
194    LiveProcess::initState();
195
196    argsInit(MachineBytes, PageBytes);
197
198    ThreadContext *tc = system->getThreadContext(contextIds[0]);
199    tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
200    //Operate in user mode
201    tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3);
202    tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3);
203    //No super page mapping
204    tc->setMiscRegNoEffect(IPR_MCSR, 0);
205}
206
207AlphaISA::IntReg
208AlphaLiveProcess::getSyscallArg(ThreadContext *tc, int &i)
209{
210    assert(i < 6);
211    return tc->readIntReg(FirstArgumentReg + i++);
212}
213
214void
215AlphaLiveProcess::setSyscallArg(ThreadContext *tc,
216        int i, AlphaISA::IntReg val)
217{
218    assert(i < 6);
219    tc->setIntReg(FirstArgumentReg + i, val);
220}
221
222void
223AlphaLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
224{
225    // check for error condition.  Alpha syscall convention is to
226    // indicate success/failure in reg a3 (r19) and put the
227    // return value itself in the standard return value reg (v0).
228    if (sysret.successful()) {
229        // no error
230        tc->setIntReg(SyscallSuccessReg, 0);
231        tc->setIntReg(ReturnValueReg, sysret.returnValue());
232    } else {
233        // got an error, return details
234        tc->setIntReg(SyscallSuccessReg, (IntReg)-1);
235        tc->setIntReg(ReturnValueReg, sysret.errnoValue());
236    }
237}
238