process.cc revision 6180
12207SN/A/* 22207SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan 32207SN/A * All rights reserved. 42207SN/A * 52207SN/A * Redistribution and use in source and binary forms, with or without 62207SN/A * modification, are permitted provided that the following conditions are 72207SN/A * met: redistributions of source code must retain the above copyright 82207SN/A * notice, this list of conditions and the following disclaimer; 92207SN/A * redistributions in binary form must reproduce the above copyright 102207SN/A * notice, this list of conditions and the following disclaimer in the 112207SN/A * documentation and/or other materials provided with the distribution; 122207SN/A * neither the name of the copyright holders nor the names of its 132207SN/A * contributors may be used to endorse or promote products derived from 142207SN/A * this software without specific prior written permission. 152207SN/A * 162207SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172207SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202207SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222207SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242207SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252207SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262207SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Ali Saidi 302207SN/A */ 312207SN/A 322972Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 332207SN/A#include "arch/alpha/process.hh" 342454SN/A#include "base/loader/object_file.hh" 355759Shsul@eecs.umich.edu#include "base/loader/elf_object.hh" 362454SN/A#include "base/misc.hh" 372680Sktlim@umich.edu#include "cpu/thread_context.hh" 385759Shsul@eecs.umich.edu#include "mem/page_table.hh" 395759Shsul@eecs.umich.edu#include "sim/process_impl.hh" 402474SN/A#include "sim/system.hh" 412207SN/A 422474SN/Ausing namespace AlphaISA; 432474SN/Ausing namespace std; 442474SN/A 455569Snate@binkert.orgAlphaLiveProcess::AlphaLiveProcess(LiveProcessParams *params, 465569Snate@binkert.org ObjectFile *objFile) 475154Sgblack@eecs.umich.edu : LiveProcess(params, objFile) 482474SN/A{ 492474SN/A brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 502474SN/A brk_point = roundUp(brk_point, VMPageSize); 512474SN/A 522474SN/A // Set up stack. On Alpha, stack goes below text section. This 532474SN/A // code should get moved to some architecture-specific spot. 542474SN/A stack_base = objFile->textBase() - (409600+4096); 552474SN/A 562474SN/A // Set up region for mmaps. Tru64 seems to start just above 0 and 572474SN/A // grow up from there. 582474SN/A mmap_start = mmap_end = 0x10000; 592474SN/A 602474SN/A // Set pointer for next thread stack. Reserve 8M for main stack. 612474SN/A next_thread_stack_base = stack_base - (8 * 1024 * 1024); 622474SN/A 632474SN/A} 642474SN/A 652474SN/Avoid 665759Shsul@eecs.umich.eduAlphaLiveProcess::argsInit(int intSize, int pageSize) 675759Shsul@eecs.umich.edu{ 685759Shsul@eecs.umich.edu objFile->loadSections(initVirtMem); 695759Shsul@eecs.umich.edu 705771Shsul@eecs.umich.edu typedef AuxVector<uint64_t> auxv_t; 715759Shsul@eecs.umich.edu std::vector<auxv_t> auxv; 725759Shsul@eecs.umich.edu 735759Shsul@eecs.umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 745759Shsul@eecs.umich.edu if(elfObject) 755759Shsul@eecs.umich.edu { 765759Shsul@eecs.umich.edu // modern glibc uses a bunch of auxiliary vectors to set up 775759Shsul@eecs.umich.edu // TLS as well as do a bunch of other stuff 785759Shsul@eecs.umich.edu // these vectors go on the bottom of the stack, below argc/argv/envp 795759Shsul@eecs.umich.edu // pointers but above actual arg strings 805759Shsul@eecs.umich.edu // I don't have all the ones glibc looks at here, but so far it doesn't 815759Shsul@eecs.umich.edu // seem to be a problem. 825759Shsul@eecs.umich.edu // check out _dl_aux_init() in glibc/elf/dl-support.c for details 835759Shsul@eecs.umich.edu // --Lisa 845759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::VMPageSize)); 855759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 865759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 875759Shsul@eecs.umich.edu DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable()); 885759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 895759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 905759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_UID, uid())); 915759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EUID, euid())); 925759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_GID, gid())); 935759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EGID, egid())); 945759Shsul@eecs.umich.edu 955759Shsul@eecs.umich.edu } 965759Shsul@eecs.umich.edu 975759Shsul@eecs.umich.edu // Calculate how much space we need for arg & env & auxv arrays. 985759Shsul@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 995759Shsul@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 1005759Shsul@eecs.umich.edu int auxv_array_size = intSize * 2 * (auxv.size() + 1); 1015759Shsul@eecs.umich.edu 1025759Shsul@eecs.umich.edu int arg_data_size = 0; 1035759Shsul@eecs.umich.edu for (int i = 0; i < argv.size(); ++i) { 1045759Shsul@eecs.umich.edu arg_data_size += argv[i].size() + 1; 1055759Shsul@eecs.umich.edu } 1065759Shsul@eecs.umich.edu int env_data_size = 0; 1075759Shsul@eecs.umich.edu for (int i = 0; i < envp.size(); ++i) { 1085759Shsul@eecs.umich.edu env_data_size += envp[i].size() + 1; 1095759Shsul@eecs.umich.edu } 1105759Shsul@eecs.umich.edu 1115759Shsul@eecs.umich.edu int space_needed = 1125759Shsul@eecs.umich.edu argv_array_size + 1135759Shsul@eecs.umich.edu envp_array_size + 1145759Shsul@eecs.umich.edu auxv_array_size + 1155759Shsul@eecs.umich.edu arg_data_size + 1165759Shsul@eecs.umich.edu env_data_size; 1175759Shsul@eecs.umich.edu 1185759Shsul@eecs.umich.edu if (space_needed < 32*1024) 1195759Shsul@eecs.umich.edu space_needed = 32*1024; 1205759Shsul@eecs.umich.edu 1215759Shsul@eecs.umich.edu // set bottom of stack 1225759Shsul@eecs.umich.edu stack_min = stack_base - space_needed; 1235759Shsul@eecs.umich.edu // align it 1245759Shsul@eecs.umich.edu stack_min = roundDown(stack_min, pageSize); 1255759Shsul@eecs.umich.edu stack_size = stack_base - stack_min; 1265759Shsul@eecs.umich.edu // map memory 1275759Shsul@eecs.umich.edu pTable->allocate(stack_min, roundUp(stack_size, pageSize)); 1285759Shsul@eecs.umich.edu 1295759Shsul@eecs.umich.edu // map out initial stack contents 1305759Shsul@eecs.umich.edu Addr argv_array_base = stack_min + intSize; // room for argc 1315759Shsul@eecs.umich.edu Addr envp_array_base = argv_array_base + argv_array_size; 1325759Shsul@eecs.umich.edu Addr auxv_array_base = envp_array_base + envp_array_size; 1335759Shsul@eecs.umich.edu Addr arg_data_base = auxv_array_base + auxv_array_size; 1345759Shsul@eecs.umich.edu Addr env_data_base = arg_data_base + arg_data_size; 1355759Shsul@eecs.umich.edu 1365759Shsul@eecs.umich.edu // write contents to stack 1375759Shsul@eecs.umich.edu uint64_t argc = argv.size(); 1385759Shsul@eecs.umich.edu if (intSize == 8) 1395759Shsul@eecs.umich.edu argc = htog((uint64_t)argc); 1405759Shsul@eecs.umich.edu else if (intSize == 4) 1415759Shsul@eecs.umich.edu argc = htog((uint32_t)argc); 1425759Shsul@eecs.umich.edu else 1435759Shsul@eecs.umich.edu panic("Unknown int size"); 1445759Shsul@eecs.umich.edu 1455759Shsul@eecs.umich.edu initVirtMem->writeBlob(stack_min, (uint8_t*)&argc, intSize); 1465759Shsul@eecs.umich.edu 1475759Shsul@eecs.umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 1485759Shsul@eecs.umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 1495759Shsul@eecs.umich.edu 1505759Shsul@eecs.umich.edu //Copy the aux stuff 1515759Shsul@eecs.umich.edu for(int x = 0; x < auxv.size(); x++) 1525759Shsul@eecs.umich.edu { 1535759Shsul@eecs.umich.edu initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, 1545759Shsul@eecs.umich.edu (uint8_t*)&(auxv[x].a_type), intSize); 1555759Shsul@eecs.umich.edu initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 1565759Shsul@eecs.umich.edu (uint8_t*)&(auxv[x].a_val), intSize); 1575759Shsul@eecs.umich.edu } 1585759Shsul@eecs.umich.edu 1595759Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1605759Shsul@eecs.umich.edu 1615958Sgblack@eecs.umich.edu setSyscallArg(tc, 0, argc); 1625958Sgblack@eecs.umich.edu setSyscallArg(tc, 1, argv_array_base); 1635759Shsul@eecs.umich.edu tc->setIntReg(StackPointerReg, stack_min); 1645759Shsul@eecs.umich.edu 1655759Shsul@eecs.umich.edu Addr prog_entry = objFile->entryPoint(); 1665759Shsul@eecs.umich.edu tc->setPC(prog_entry); 1675759Shsul@eecs.umich.edu tc->setNextPC(prog_entry + sizeof(MachInst)); 1685759Shsul@eecs.umich.edu 1696180Sksewell@umich.edu // MIPS/Sparc need NNPC for delay slot handling, while 1706180Sksewell@umich.edu // Alpha has no delay slots... However, CPU models 1716180Sksewell@umich.edu // cycle PCs by PC=NPC, NPC=NNPC, etc. so setting this 1726180Sksewell@umich.edu // here ensures CPU-Model Compatibility across board 1735759Shsul@eecs.umich.edu tc->setNextNPC(prog_entry + (2 * sizeof(MachInst))); 1745759Shsul@eecs.umich.edu} 1755759Shsul@eecs.umich.edu 1765759Shsul@eecs.umich.eduvoid 1772474SN/AAlphaLiveProcess::startup() 1782474SN/A{ 1795183Ssaidi@eecs.umich.edu if (checkpointRestored) 1805183Ssaidi@eecs.umich.edu return; 1815183Ssaidi@eecs.umich.edu 1825759Shsul@eecs.umich.edu Process::startup(); 1835759Shsul@eecs.umich.edu 1842474SN/A argsInit(MachineBytes, VMPageSize); 1852474SN/A 1865713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1875713Shsul@eecs.umich.edu tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); 1885713Shsul@eecs.umich.edu //Operate in user mode 1895713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(IPR_ICM, 0x18); 1904997Sgblack@eecs.umich.edu //No super page mapping 1915713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(IPR_MCSR, 0); 1924997Sgblack@eecs.umich.edu //Set this to 0 for now, but it should be unique for each process 1935713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57); 1942474SN/A} 1952474SN/A 1965958Sgblack@eecs.umich.eduAlphaISA::IntReg 1975958Sgblack@eecs.umich.eduAlphaLiveProcess::getSyscallArg(ThreadContext *tc, int i) 1985958Sgblack@eecs.umich.edu{ 1995958Sgblack@eecs.umich.edu assert(i < 6); 2005958Sgblack@eecs.umich.edu return tc->readIntReg(FirstArgumentReg + i); 2015958Sgblack@eecs.umich.edu} 2025958Sgblack@eecs.umich.edu 2035958Sgblack@eecs.umich.eduvoid 2045958Sgblack@eecs.umich.eduAlphaLiveProcess::setSyscallArg(ThreadContext *tc, 2055958Sgblack@eecs.umich.edu int i, AlphaISA::IntReg val) 2065958Sgblack@eecs.umich.edu{ 2075958Sgblack@eecs.umich.edu assert(i < 6); 2085958Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, val); 2095958Sgblack@eecs.umich.edu} 2105958Sgblack@eecs.umich.edu 2115958Sgblack@eecs.umich.eduvoid 2125958Sgblack@eecs.umich.eduAlphaLiveProcess::setSyscallReturn(ThreadContext *tc, 2135958Sgblack@eecs.umich.edu SyscallReturn return_value) 2145958Sgblack@eecs.umich.edu{ 2155958Sgblack@eecs.umich.edu // check for error condition. Alpha syscall convention is to 2165958Sgblack@eecs.umich.edu // indicate success/failure in reg a3 (r19) and put the 2175958Sgblack@eecs.umich.edu // return value itself in the standard return value reg (v0). 2185958Sgblack@eecs.umich.edu if (return_value.successful()) { 2195958Sgblack@eecs.umich.edu // no error 2205958Sgblack@eecs.umich.edu tc->setIntReg(SyscallSuccessReg, 0); 2215958Sgblack@eecs.umich.edu tc->setIntReg(ReturnValueReg, return_value.value()); 2225958Sgblack@eecs.umich.edu } else { 2235958Sgblack@eecs.umich.edu // got an error, return details 2245958Sgblack@eecs.umich.edu tc->setIntReg(SyscallSuccessReg, (IntReg)-1); 2255958Sgblack@eecs.umich.edu tc->setIntReg(ReturnValueReg, -return_value.value()); 2265958Sgblack@eecs.umich.edu } 2275958Sgblack@eecs.umich.edu} 228