process.cc revision 5183
12207SN/A/*
22207SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan
32207SN/A * All rights reserved.
42207SN/A *
52207SN/A * Redistribution and use in source and binary forms, with or without
62207SN/A * modification, are permitted provided that the following conditions are
72207SN/A * met: redistributions of source code must retain the above copyright
82207SN/A * notice, this list of conditions and the following disclaimer;
92207SN/A * redistributions in binary form must reproduce the above copyright
102207SN/A * notice, this list of conditions and the following disclaimer in the
112207SN/A * documentation and/or other materials provided with the distribution;
122207SN/A * neither the name of the copyright holders nor the names of its
132207SN/A * contributors may be used to endorse or promote products derived from
142207SN/A * this software without specific prior written permission.
152207SN/A *
162207SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172207SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202207SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222207SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242207SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252207SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262207SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Gabe Black
292665Ssaidi@eecs.umich.edu *          Ali Saidi
302207SN/A */
312207SN/A
322972Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh"
332207SN/A#include "arch/alpha/process.hh"
342454SN/A#include "base/loader/object_file.hh"
352454SN/A#include "base/misc.hh"
362680Sktlim@umich.edu#include "cpu/thread_context.hh"
372474SN/A#include "sim/system.hh"
382207SN/A
392207SN/A
402474SN/Ausing namespace AlphaISA;
412474SN/Ausing namespace std;
422474SN/A
435154Sgblack@eecs.umich.eduAlphaLiveProcess::AlphaLiveProcess(LiveProcessParams * params,
445154Sgblack@eecs.umich.edu        ObjectFile *objFile)
455154Sgblack@eecs.umich.edu    : LiveProcess(params, objFile)
462474SN/A{
472474SN/A    brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
482474SN/A    brk_point = roundUp(brk_point, VMPageSize);
492474SN/A
502474SN/A    // Set up stack.  On Alpha, stack goes below text section.  This
512474SN/A    // code should get moved to some architecture-specific spot.
522474SN/A    stack_base = objFile->textBase() - (409600+4096);
532474SN/A
542474SN/A    // Set up region for mmaps.  Tru64 seems to start just above 0 and
552474SN/A    // grow up from there.
562474SN/A    mmap_start = mmap_end = 0x10000;
572474SN/A
582474SN/A    // Set pointer for next thread stack.  Reserve 8M for main stack.
592474SN/A    next_thread_stack_base = stack_base - (8 * 1024 * 1024);
602474SN/A
612474SN/A}
622474SN/A
632474SN/Avoid
642474SN/AAlphaLiveProcess::startup()
652474SN/A{
665183Ssaidi@eecs.umich.edu    if (checkpointRestored)
675183Ssaidi@eecs.umich.edu        return;
685183Ssaidi@eecs.umich.edu
692474SN/A    argsInit(MachineBytes, VMPageSize);
702474SN/A
712680Sktlim@umich.edu    threadContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer());
724997Sgblack@eecs.umich.edu    //Opperate in user mode
734997Sgblack@eecs.umich.edu    threadContexts[0]->setMiscRegNoEffect(IPR_ICM, 0x18);
744997Sgblack@eecs.umich.edu    //No super page mapping
754997Sgblack@eecs.umich.edu    threadContexts[0]->setMiscRegNoEffect(IPR_MCSR, 0);
764997Sgblack@eecs.umich.edu    //Set this to 0 for now, but it should be unique for each process
774997Sgblack@eecs.umich.edu    threadContexts[0]->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
782474SN/A}
792474SN/A
802474SN/A
81