main.isa revision 9918:2c7219e2d999
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// Alpha ISA description file.
34//
35////////////////////////////////////////////////////////////////////
36
37
38////////////////////////////////////////////////////////////////////
39//
40// Output include file directives.
41//
42
43output header {{
44#include <iomanip>
45#include <iostream>
46#include <sstream>
47
48#include "arch/alpha/faults.hh"
49#include "arch/alpha/types.hh"
50#include "config/ss_compatible_fp.hh"
51#include "cpu/static_inst.hh"
52#include "mem/packet.hh"
53#include "mem/request.hh"  // some constructors use MemReq flags
54}};
55
56output decoder {{
57#include <cmath>
58
59#include "arch/alpha/decoder.hh"
60#include "arch/alpha/registers.hh"
61#include "arch/alpha/regredir.hh"
62#include "base/loader/symtab.hh"
63#include "base/cprintf.hh"
64#include "base/fenv.hh"
65#include "config/ss_compatible_fp.hh"
66#include "cpu/thread_context.hh"  // for Jump::branchTarget()
67#include "mem/packet.hh"
68#include "sim/full_system.hh"
69
70using namespace AlphaISA;
71}};
72
73output exec {{
74#include <cmath>
75
76#include "arch/alpha/decoder.hh"
77#include "arch/alpha/registers.hh"
78#include "arch/alpha/regredir.hh"
79#include "arch/generic/memhelpers.hh"
80#include "base/cp_annotate.hh"
81#include "base/fenv.hh"
82#include "config/ss_compatible_fp.hh"
83#include "cpu/base.hh"
84#include "cpu/exetrace.hh"
85#include "mem/packet.hh"
86#include "mem/packet_access.hh"
87#include "sim/full_system.hh"
88#include "sim/pseudo_inst.hh"
89#include "sim/sim_exit.hh"
90
91using namespace AlphaISA;
92}};
93
94////////////////////////////////////////////////////////////////////
95//
96// Namespace statement.  Everything below this line will be in the
97// AlphaISAInst namespace.
98//
99
100
101namespace AlphaISA;
102
103////////////////////////////////////////////////////////////////////
104//
105// Bitfield definitions.
106//
107
108// Universal (format-independent) fields
109def bitfield PALMODE    <32:32>;
110def bitfield OPCODE     <31:26>;
111def bitfield RA         <25:21>;
112def bitfield RB         <20:16>;
113
114// Memory format
115def signed bitfield MEMDISP <15: 0>; // displacement
116def        bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
117
118// Memory-format jumps
119def bitfield JMPFUNC    <15:14>; // function code (disp<15:14>)
120def bitfield JMPHINT    <13: 0>; // tgt Icache idx hint (disp<13:0>)
121
122// Branch format
123def signed bitfield BRDISP <20: 0>; // displacement
124
125// Integer operate format(s>;
126def bitfield INTIMM     <20:13>; // integer immediate (literal)
127def bitfield IMM        <12:12>; // immediate flag
128def bitfield INTFUNC    <11: 5>; // function code
129def bitfield RC         < 4: 0>; // dest reg
130
131// Floating-point operate format
132def bitfield FA           <25:21>;
133def bitfield FB           <20:16>;
134def bitfield FP_FULLFUNC  <15: 5>; // complete function code
135    def bitfield FP_TRAPMODE  <15:13>; // trapping mode
136    def bitfield FP_ROUNDMODE <12:11>; // rounding mode
137    def bitfield FP_TYPEFUNC  <10: 5>; // type+func: handiest for decoding
138        def bitfield FP_SRCTYPE   <10: 9>; // source reg type
139        def bitfield FP_SHORTFUNC < 8: 5>; // short function code
140        def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
141def bitfield FC           < 4: 0>; // dest reg
142
143// PALcode format
144def bitfield PALFUNC    <25: 0>; // function code
145
146// EV5 PAL instructions:
147// HW_LD/HW_ST
148def bitfield HW_LDST_PHYS  <15>; // address is physical
149def bitfield HW_LDST_ALT   <14>; // use ALT_MODE IPR
150def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
151def bitfield HW_LDST_QUAD  <12>; // size: 0=32b, 1=64b
152def bitfield HW_LDST_VPTE  <11>; // HW_LD only: is PTE fetch
153def bitfield HW_LDST_LOCK  <10>; // HW_LD only: is load locked
154def bitfield HW_LDST_COND  <10>; // HW_ST only: is store conditional
155def signed bitfield HW_LDST_DISP  <9:0>; // signed displacement
156
157// HW_REI
158def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
159def bitfield HW_REI_MBZ <13: 0>; // must be zero
160
161// HW_MTPR/MW_MFPR
162def bitfield HW_IPR_IDX <15:0>;  // IPR index
163
164// M5 instructions
165def bitfield M5FUNC <7:0>;
166
167def operand_types {{
168    'sb' : 'int8_t',
169    'ub' : 'uint8_t',
170    'sw' : 'int16_t',
171    'uw' : 'uint16_t',
172    'sl' : 'int32_t',
173    'ul' : 'uint32_t',
174    'sq' : 'int64_t',
175    'uq' : 'uint64_t',
176    'sf' : 'float',
177    'df' : 'double'
178}};
179
180def operands {{
181    # Int regs default to unsigned, but code should not count on this.
182    # For clarity, descriptions that depend on unsigned behavior should
183    # explicitly specify '_uq'.
184    'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
185           'IsInteger', 1),
186    'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
187           'IsInteger', 2),
188    'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
189           'IsInteger', 3),
190    'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
191    'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
192    'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
193    'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
194    'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4),
195    'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4),
196    'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
197    'FPCR':  ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
198    'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
199    # The next two are hacks for non-full-system call-pal emulation
200    'R0':  ('IntReg', 'uq', '0', None, 1),
201    'R16': ('IntReg', 'uq', '16', None, 1),
202    'R17': ('IntReg', 'uq', '17', None, 1),
203    'R18': ('IntReg', 'uq', '18', None, 1)
204}};
205
206////////////////////////////////////////////////////////////////////
207//
208// Basic instruction classes/templates/formats etc.
209//
210
211output header {{
212// uncomment the following to get SimpleScalar-compatible disassembly
213// (useful for diffing output traces).
214// #define SS_COMPATIBLE_DISASSEMBLY
215
216    /**
217     * Base class for all Alpha static instructions.
218     */
219    class AlphaStaticInst : public StaticInst
220    {
221      protected:
222
223        /// Make AlphaISA register dependence tags directly visible in
224        /// this class and derived classes.  Maybe these should really
225        /// live here and not in the AlphaISA namespace.
226        enum DependenceTags {
227            FP_Reg_Base = AlphaISA::FP_Reg_Base
228        };
229
230        /// Constructor.
231        AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
232                        OpClass __opClass)
233            : StaticInst(mnem, _machInst, __opClass)
234        {
235        }
236
237        /// Print a register name for disassembly given the unique
238        /// dependence tag number (FP or int).
239        void printReg(std::ostream &os, int reg) const;
240
241        std::string
242        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
243
244        void
245        advancePC(AlphaISA::PCState &pcState) const
246        {
247            pcState.advance();
248        }
249    };
250}};
251
252output decoder {{
253    void
254    AlphaStaticInst::printReg(std::ostream &os, int reg) const
255    {
256        if (reg < FP_Reg_Base) {
257            ccprintf(os, "r%d", reg);
258        }
259        else {
260            ccprintf(os, "f%d", reg - FP_Reg_Base);
261        }
262    }
263
264    std::string
265    AlphaStaticInst::generateDisassembly(Addr pc,
266                                         const SymbolTable *symtab) const
267    {
268        std::stringstream ss;
269
270        ccprintf(ss, "%-10s ", mnemonic);
271
272        // just print the first two source regs... if there's
273        // a third one, it's a read-modify-write dest (Rc),
274        // e.g. for CMOVxx
275        if (_numSrcRegs > 0) {
276            printReg(ss, _srcRegIdx[0]);
277        }
278        if (_numSrcRegs > 1) {
279            ss << ",";
280            printReg(ss, _srcRegIdx[1]);
281        }
282
283        // just print the first dest... if there's a second one,
284        // it's generally implicit
285        if (_numDestRegs > 0) {
286            if (_numSrcRegs > 0)
287                ss << ",";
288            printReg(ss, _destRegIdx[0]);
289        }
290
291        return ss.str();
292    }
293}};
294
295// Declarations for execute() methods.
296def template BasicExecDeclare {{
297    Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
298}};
299
300// Basic instruction class declaration template.
301def template BasicDeclare {{
302    /**
303     * Static instruction class for "%(mnemonic)s".
304     */
305    class %(class_name)s : public %(base_class)s
306    {
307      public:
308        /// Constructor.
309        %(class_name)s(ExtMachInst machInst);
310
311        %(BasicExecDeclare)s
312    };
313}};
314
315// Basic instruction class constructor template.
316def template BasicConstructor {{
317    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
318         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
319    {
320        %(constructor)s;
321    }
322}};
323
324// Basic instruction class execute method template.
325def template BasicExecute {{
326    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
327                                  Trace::InstRecord *traceData) const
328    {
329        Fault fault = NoFault;
330
331        %(fp_enable_check)s;
332        %(op_decl)s;
333        %(op_rd)s;
334        %(code)s;
335
336        if (fault == NoFault) {
337            %(op_wb)s;
338        }
339
340        return fault;
341    }
342}};
343
344// Basic decode template.
345def template BasicDecode {{
346    return new %(class_name)s(machInst);
347}};
348
349// Basic decode template, passing mnemonic in as string arg to constructor.
350def template BasicDecodeWithMnemonic {{
351    return new %(class_name)s("%(mnemonic)s", machInst);
352}};
353
354// The most basic instruction format... used only for a few misc. insts
355def format BasicOperate(code, *flags) {{
356    iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
357    header_output = BasicDeclare.subst(iop)
358    decoder_output = BasicConstructor.subst(iop)
359    decode_block = BasicDecode.subst(iop)
360    exec_output = BasicExecute.subst(iop)
361}};
362
363
364
365////////////////////////////////////////////////////////////////////
366//
367// Nop
368//
369
370output header {{
371    /**
372     * Static instruction class for no-ops.  This is a leaf class.
373     */
374    class Nop : public AlphaStaticInst
375    {
376        /// Disassembly of original instruction.
377        const std::string originalDisassembly;
378
379      public:
380        /// Constructor
381        Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
382            : AlphaStaticInst("nop", _machInst, No_OpClass),
383              originalDisassembly(_originalDisassembly)
384        {
385            flags[IsNop] = true;
386        }
387
388        ~Nop() { }
389
390        std::string
391        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
392
393        %(BasicExecDeclare)s
394    };
395
396    /// Helper function for decoding nops.  Substitute Nop object
397    /// for original inst passed in as arg (and delete latter).
398    static inline
399    AlphaStaticInst *
400    makeNop(AlphaStaticInst *inst)
401    {
402        AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
403        delete inst;
404        return nop;
405    }
406}};
407
408output decoder {{
409    std::string Nop::generateDisassembly(Addr pc,
410                                         const SymbolTable *symtab) const
411    {
412#ifdef SS_COMPATIBLE_DISASSEMBLY
413        return originalDisassembly;
414#else
415        return csprintf("%-10s (%s)", "nop", originalDisassembly);
416#endif
417    }
418}};
419
420output exec {{
421    Fault
422    Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
423    {
424        return NoFault;
425    }
426}};
427
428// integer & FP operate instructions use Rc as dest, so check for
429// Rc == 31 to detect nops
430def template OperateNopCheckDecode {{
431 {
432     AlphaStaticInst *i = new %(class_name)s(machInst);
433     if (RC == 31) {
434         i = makeNop(i);
435     }
436     return i;
437 }
438}};
439
440// Like BasicOperate format, but generates NOP if RC/FC == 31
441def format BasicOperateWithNopCheck(code, *opt_args) {{
442    iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
443    header_output = BasicDeclare.subst(iop)
444    decoder_output = BasicConstructor.subst(iop)
445    decode_block = OperateNopCheckDecode.subst(iop)
446    exec_output = BasicExecute.subst(iop)
447}};
448
449// Integer instruction templates, formats, etc.
450##include "int.isa"
451
452// Floating-point instruction templates, formats, etc.
453##include "fp.isa"
454
455// Memory instruction templates, formats, etc.
456##include "mem.isa"
457
458// Branch/jump instruction templates, formats, etc.
459##include "branch.isa"
460
461// PAL instruction templates, formats, etc.
462##include "pal.isa"
463
464// Opcdec fault instruction templates, formats, etc.
465##include "opcdec.isa"
466
467// Unimplemented instruction templates, formats, etc.
468##include "unimp.isa"
469
470// Unknown instruction templates, formats, etc.
471##include "unknown.isa"
472
473// Execution utility functions
474##include "util.isa"
475
476// The actual decoder
477##include "decoder.isa"
478