main.isa revision 8738:66bf413b0d5b
1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2005 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// Alpha ISA description file. 34// 35//////////////////////////////////////////////////////////////////// 36 37 38//////////////////////////////////////////////////////////////////// 39// 40// Output include file directives. 41// 42 43output header {{ 44#include <iomanip> 45#include <iostream> 46#include <sstream> 47 48#include "arch/alpha/faults.hh" 49#include "arch/alpha/types.hh" 50#include "config/ss_compatible_fp.hh" 51#include "cpu/static_inst.hh" 52#include "mem/packet.hh" 53#include "mem/request.hh" // some constructors use MemReq flags 54}}; 55 56output decoder {{ 57#include <cmath> 58 59#include "arch/alpha/registers.hh" 60#include "arch/alpha/regredir.hh" 61#include "base/loader/symtab.hh" 62#include "base/cprintf.hh" 63#include "base/fenv.hh" 64#include "config/ss_compatible_fp.hh" 65#include "cpu/thread_context.hh" // for Jump::branchTarget() 66#include "mem/packet.hh" 67#include "sim/full_system.hh" 68 69using namespace AlphaISA; 70}}; 71 72output exec {{ 73#include <math.h> 74 75#include "arch/alpha/registers.hh" 76#include "arch/alpha/regredir.hh" 77#include "arch/generic/memhelpers.hh" 78#include "base/cp_annotate.hh" 79#include "base/fenv.hh" 80#include "config/ss_compatible_fp.hh" 81#include "cpu/base.hh" 82#include "cpu/exetrace.hh" 83#include "mem/packet.hh" 84#include "mem/packet_access.hh" 85#include "sim/full_system.hh" 86#include "sim/pseudo_inst.hh" 87#include "sim/sim_exit.hh" 88 89using namespace AlphaISA; 90}}; 91 92//////////////////////////////////////////////////////////////////// 93// 94// Namespace statement. Everything below this line will be in the 95// AlphaISAInst namespace. 96// 97 98 99namespace AlphaISA; 100 101//////////////////////////////////////////////////////////////////// 102// 103// Bitfield definitions. 104// 105 106// Universal (format-independent) fields 107def bitfield PALMODE <32:32>; 108def bitfield OPCODE <31:26>; 109def bitfield RA <25:21>; 110def bitfield RB <20:16>; 111 112// Memory format 113def signed bitfield MEMDISP <15: 0>; // displacement 114def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned) 115 116// Memory-format jumps 117def bitfield JMPFUNC <15:14>; // function code (disp<15:14>) 118def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>) 119 120// Branch format 121def signed bitfield BRDISP <20: 0>; // displacement 122 123// Integer operate format(s>; 124def bitfield INTIMM <20:13>; // integer immediate (literal) 125def bitfield IMM <12:12>; // immediate flag 126def bitfield INTFUNC <11: 5>; // function code 127def bitfield RC < 4: 0>; // dest reg 128 129// Floating-point operate format 130def bitfield FA <25:21>; 131def bitfield FB <20:16>; 132def bitfield FP_FULLFUNC <15: 5>; // complete function code 133 def bitfield FP_TRAPMODE <15:13>; // trapping mode 134 def bitfield FP_ROUNDMODE <12:11>; // rounding mode 135 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding 136 def bitfield FP_SRCTYPE <10: 9>; // source reg type 137 def bitfield FP_SHORTFUNC < 8: 5>; // short function code 138 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code 139def bitfield FC < 4: 0>; // dest reg 140 141// PALcode format 142def bitfield PALFUNC <25: 0>; // function code 143 144// EV5 PAL instructions: 145// HW_LD/HW_ST 146def bitfield HW_LDST_PHYS <15>; // address is physical 147def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR 148def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc 149def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b 150def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch 151def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked 152def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional 153def signed bitfield HW_LDST_DISP <9:0>; // signed displacement 154 155// HW_REI 156def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk 157def bitfield HW_REI_MBZ <13: 0>; // must be zero 158 159// HW_MTPR/MW_MFPR 160def bitfield HW_IPR_IDX <15:0>; // IPR index 161 162// M5 instructions 163def bitfield M5FUNC <7:0>; 164 165def operand_types {{ 166 'sb' : 'int8_t', 167 'ub' : 'uint8_t', 168 'sw' : 'int16_t', 169 'uw' : 'uint16_t', 170 'sl' : 'int32_t', 171 'ul' : 'uint32_t', 172 'sq' : 'int64_t', 173 'uq' : 'uint64_t', 174 'sf' : 'float', 175 'df' : 'double' 176}}; 177 178def operands {{ 179 # Int regs default to unsigned, but code should not count on this. 180 # For clarity, descriptions that depend on unsigned behavior should 181 # explicitly specify '_uq'. 182 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA', 183 'IsInteger', 1), 184 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB', 185 'IsInteger', 2), 186 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC', 187 'IsInteger', 3), 188 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), 189 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), 190 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 191 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 192 'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4), 193 'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4), 194 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1), 195 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1), 196 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1), 197 # The next two are hacks for non-full-system call-pal emulation 198 'R0': ('IntReg', 'uq', '0', None, 1), 199 'R16': ('IntReg', 'uq', '16', None, 1), 200 'R17': ('IntReg', 'uq', '17', None, 1), 201 'R18': ('IntReg', 'uq', '18', None, 1) 202}}; 203 204//////////////////////////////////////////////////////////////////// 205// 206// Basic instruction classes/templates/formats etc. 207// 208 209output header {{ 210// uncomment the following to get SimpleScalar-compatible disassembly 211// (useful for diffing output traces). 212// #define SS_COMPATIBLE_DISASSEMBLY 213 214 /** 215 * Base class for all Alpha static instructions. 216 */ 217 class AlphaStaticInst : public StaticInst 218 { 219 protected: 220 221 /// Make AlphaISA register dependence tags directly visible in 222 /// this class and derived classes. Maybe these should really 223 /// live here and not in the AlphaISA namespace. 224 enum DependenceTags { 225 FP_Base_DepTag = AlphaISA::FP_Base_DepTag, 226 }; 227 228 /// Constructor. 229 AlphaStaticInst(const char *mnem, ExtMachInst _machInst, 230 OpClass __opClass) 231 : StaticInst(mnem, _machInst, __opClass) 232 { 233 } 234 235 /// Print a register name for disassembly given the unique 236 /// dependence tag number (FP or int). 237 void printReg(std::ostream &os, int reg) const; 238 239 std::string 240 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 241 242 void 243 advancePC(AlphaISA::PCState &pcState) const 244 { 245 pcState.advance(); 246 } 247 }; 248}}; 249 250output decoder {{ 251 void 252 AlphaStaticInst::printReg(std::ostream &os, int reg) const 253 { 254 if (reg < FP_Base_DepTag) { 255 ccprintf(os, "r%d", reg); 256 } 257 else { 258 ccprintf(os, "f%d", reg - FP_Base_DepTag); 259 } 260 } 261 262 std::string 263 AlphaStaticInst::generateDisassembly(Addr pc, 264 const SymbolTable *symtab) const 265 { 266 std::stringstream ss; 267 268 ccprintf(ss, "%-10s ", mnemonic); 269 270 // just print the first two source regs... if there's 271 // a third one, it's a read-modify-write dest (Rc), 272 // e.g. for CMOVxx 273 if (_numSrcRegs > 0) { 274 printReg(ss, _srcRegIdx[0]); 275 } 276 if (_numSrcRegs > 1) { 277 ss << ","; 278 printReg(ss, _srcRegIdx[1]); 279 } 280 281 // just print the first dest... if there's a second one, 282 // it's generally implicit 283 if (_numDestRegs > 0) { 284 if (_numSrcRegs > 0) 285 ss << ","; 286 printReg(ss, _destRegIdx[0]); 287 } 288 289 return ss.str(); 290 } 291}}; 292 293// Declarations for execute() methods. 294def template BasicExecDeclare {{ 295 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; 296}}; 297 298// Basic instruction class declaration template. 299def template BasicDeclare {{ 300 /** 301 * Static instruction class for "%(mnemonic)s". 302 */ 303 class %(class_name)s : public %(base_class)s 304 { 305 public: 306 /// Constructor. 307 %(class_name)s(ExtMachInst machInst); 308 309 %(BasicExecDeclare)s 310 }; 311}}; 312 313// Basic instruction class constructor template. 314def template BasicConstructor {{ 315 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 316 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 317 { 318 %(constructor)s; 319 } 320}}; 321 322// Basic instruction class execute method template. 323def template BasicExecute {{ 324 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 325 Trace::InstRecord *traceData) const 326 { 327 Fault fault = NoFault; 328 329 %(fp_enable_check)s; 330 %(op_decl)s; 331 %(op_rd)s; 332 %(code)s; 333 334 if (fault == NoFault) { 335 %(op_wb)s; 336 } 337 338 return fault; 339 } 340}}; 341 342// Basic decode template. 343def template BasicDecode {{ 344 return new %(class_name)s(machInst); 345}}; 346 347// Basic decode template, passing mnemonic in as string arg to constructor. 348def template BasicDecodeWithMnemonic {{ 349 return new %(class_name)s("%(mnemonic)s", machInst); 350}}; 351 352// The most basic instruction format... used only for a few misc. insts 353def format BasicOperate(code, *flags) {{ 354 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags) 355 header_output = BasicDeclare.subst(iop) 356 decoder_output = BasicConstructor.subst(iop) 357 decode_block = BasicDecode.subst(iop) 358 exec_output = BasicExecute.subst(iop) 359}}; 360 361 362 363//////////////////////////////////////////////////////////////////// 364// 365// Nop 366// 367 368output header {{ 369 /** 370 * Static instruction class for no-ops. This is a leaf class. 371 */ 372 class Nop : public AlphaStaticInst 373 { 374 /// Disassembly of original instruction. 375 const std::string originalDisassembly; 376 377 public: 378 /// Constructor 379 Nop(const std::string _originalDisassembly, ExtMachInst _machInst) 380 : AlphaStaticInst("nop", _machInst, No_OpClass), 381 originalDisassembly(_originalDisassembly) 382 { 383 flags[IsNop] = true; 384 } 385 386 ~Nop() { } 387 388 std::string 389 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 390 391 %(BasicExecDeclare)s 392 }; 393 394 /// Helper function for decoding nops. Substitute Nop object 395 /// for original inst passed in as arg (and delete latter). 396 static inline 397 AlphaStaticInst * 398 makeNop(AlphaStaticInst *inst) 399 { 400 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst); 401 delete inst; 402 return nop; 403 } 404}}; 405 406output decoder {{ 407 std::string Nop::generateDisassembly(Addr pc, 408 const SymbolTable *symtab) const 409 { 410#ifdef SS_COMPATIBLE_DISASSEMBLY 411 return originalDisassembly; 412#else 413 return csprintf("%-10s (%s)", "nop", originalDisassembly); 414#endif 415 } 416}}; 417 418output exec {{ 419 Fault 420 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const 421 { 422 return NoFault; 423 } 424}}; 425 426// integer & FP operate instructions use Rc as dest, so check for 427// Rc == 31 to detect nops 428def template OperateNopCheckDecode {{ 429 { 430 AlphaStaticInst *i = new %(class_name)s(machInst); 431 if (RC == 31) { 432 i = makeNop(i); 433 } 434 return i; 435 } 436}}; 437 438// Like BasicOperate format, but generates NOP if RC/FC == 31 439def format BasicOperateWithNopCheck(code, *opt_args) {{ 440 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args) 441 header_output = BasicDeclare.subst(iop) 442 decoder_output = BasicConstructor.subst(iop) 443 decode_block = OperateNopCheckDecode.subst(iop) 444 exec_output = BasicExecute.subst(iop) 445}}; 446 447// Integer instruction templates, formats, etc. 448##include "int.isa" 449 450// Floating-point instruction templates, formats, etc. 451##include "fp.isa" 452 453// Memory instruction templates, formats, etc. 454##include "mem.isa" 455 456// Branch/jump instruction templates, formats, etc. 457##include "branch.isa" 458 459// PAL instruction templates, formats, etc. 460##include "pal.isa" 461 462// Opcdec fault instruction templates, formats, etc. 463##include "opcdec.isa" 464 465// Unimplemented instruction templates, formats, etc. 466##include "unimp.isa" 467 468// Unknown instruction templates, formats, etc. 469##include "unknown.isa" 470 471// Execution utility functions 472##include "util.isa" 473 474// The actual decoder 475##include "decoder.isa" 476