main.isa revision 7720:65d338a8dba4 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// Alpha ISA description file.
34//
35////////////////////////////////////////////////////////////////////
36
37
38////////////////////////////////////////////////////////////////////
39//
40// Output include file directives.
41//
42
43output header {{
44#include <sstream>
45#include <iostream>
46#include <iomanip>
47
48#include "arch/alpha/faults.hh"
49#include "arch/alpha/types.hh"
50#include "config/ss_compatible_fp.hh"
51#include "cpu/static_inst.hh"
52#include "mem/request.hh"  // some constructors use MemReq flags
53#include "mem/packet.hh"
54}};
55
56output decoder {{
57#include <cmath>
58
59#include "arch/alpha/registers.hh"
60#include "arch/alpha/regredir.hh"
61#include "base/cprintf.hh"
62#include "base/fenv.hh"
63#include "base/loader/symtab.hh"
64#include "config/ss_compatible_fp.hh"
65#include "cpu/thread_context.hh"  // for Jump::branchTarget()
66#include "mem/packet.hh"
67
68using namespace AlphaISA;
69}};
70
71output exec {{
72#include <math.h>
73
74#include "arch/alpha/regredir.hh"
75#include "base/cp_annotate.hh"
76#include "sim/pseudo_inst.hh"
77#include "arch/alpha/registers.hh"
78#include "base/fenv.hh"
79#include "config/ss_compatible_fp.hh"
80#include "cpu/base.hh"
81#include "cpu/exetrace.hh"
82#include "mem/packet.hh"
83#include "mem/packet_access.hh"
84#include "sim/sim_exit.hh"
85
86using namespace AlphaISA;
87}};
88
89////////////////////////////////////////////////////////////////////
90//
91// Namespace statement.  Everything below this line will be in the
92// AlphaISAInst namespace.
93//
94
95
96namespace AlphaISA;
97
98////////////////////////////////////////////////////////////////////
99//
100// Bitfield definitions.
101//
102
103// Universal (format-independent) fields
104def bitfield PALMODE    <32:32>;
105def bitfield OPCODE	<31:26>;
106def bitfield RA		<25:21>;
107def bitfield RB		<20:16>;
108
109// Memory format
110def signed bitfield MEMDISP <15: 0>; // displacement
111def        bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
112
113// Memory-format jumps
114def bitfield JMPFUNC	<15:14>; // function code (disp<15:14>)
115def bitfield JMPHINT	<13: 0>; // tgt Icache idx hint (disp<13:0>)
116
117// Branch format
118def signed bitfield BRDISP <20: 0>; // displacement
119
120// Integer operate format(s>;
121def bitfield INTIMM	<20:13>; // integer immediate (literal)
122def bitfield IMM	<12:12>; // immediate flag
123def bitfield INTFUNC	<11: 5>; // function code
124def bitfield RC		< 4: 0>; // dest reg
125
126// Floating-point operate format
127def bitfield FA		  <25:21>;
128def bitfield FB		  <20:16>;
129def bitfield FP_FULLFUNC  <15: 5>; // complete function code
130    def bitfield FP_TRAPMODE  <15:13>; // trapping mode
131    def bitfield FP_ROUNDMODE <12:11>; // rounding mode
132    def bitfield FP_TYPEFUNC  <10: 5>; // type+func: handiest for decoding
133        def bitfield FP_SRCTYPE   <10: 9>; // source reg type
134        def bitfield FP_SHORTFUNC < 8: 5>; // short function code
135        def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
136def bitfield FC		  < 4: 0>; // dest reg
137
138// PALcode format
139def bitfield PALFUNC	<25: 0>; // function code
140
141// EV5 PAL instructions:
142// HW_LD/HW_ST
143def bitfield HW_LDST_PHYS  <15>; // address is physical
144def bitfield HW_LDST_ALT   <14>; // use ALT_MODE IPR
145def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
146def bitfield HW_LDST_QUAD  <12>; // size: 0=32b, 1=64b
147def bitfield HW_LDST_VPTE  <11>; // HW_LD only: is PTE fetch
148def bitfield HW_LDST_LOCK  <10>; // HW_LD only: is load locked
149def bitfield HW_LDST_COND  <10>; // HW_ST only: is store conditional
150def signed bitfield HW_LDST_DISP  <9:0>; // signed displacement
151
152// HW_REI
153def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
154def bitfield HW_REI_MBZ <13: 0>; // must be zero
155
156// HW_MTPR/MW_MFPR
157def bitfield HW_IPR_IDX <15:0>;	 // IPR index
158
159// M5 instructions
160def bitfield M5FUNC <7:0>;
161
162def operand_types {{
163    'sb' : ('signed int', 8),
164    'ub' : ('unsigned int', 8),
165    'sw' : ('signed int', 16),
166    'uw' : ('unsigned int', 16),
167    'sl' : ('signed int', 32),
168    'ul' : ('unsigned int', 32),
169    'sq' : ('signed int', 64),
170    'uq' : ('unsigned int', 64),
171    'sf' : ('float', 32),
172    'df' : ('float', 64)
173}};
174
175def operands {{
176    # Int regs default to unsigned, but code should not count on this.
177    # For clarity, descriptions that depend on unsigned behavior should
178    # explicitly specify '.uq'.
179    'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
180           'IsInteger', 1),
181    'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
182           'IsInteger', 2),
183    'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
184           'IsInteger', 3),
185    'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
186    'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
187    'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
188    'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
189    'PCS': ('PCState', 'uq', None, ( None, None, 'IsControl' ), 4),
190    'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
191    'FPCR':  ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
192    'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
193    # The next two are hacks for non-full-system call-pal emulation
194    'R0':  ('IntReg', 'uq', '0', None, 1),
195    'R16': ('IntReg', 'uq', '16', None, 1),
196    'R17': ('IntReg', 'uq', '17', None, 1),
197    'R18': ('IntReg', 'uq', '18', None, 1)
198}};
199
200////////////////////////////////////////////////////////////////////
201//
202// Basic instruction classes/templates/formats etc.
203//
204
205output header {{
206// uncomment the following to get SimpleScalar-compatible disassembly
207// (useful for diffing output traces).
208// #define SS_COMPATIBLE_DISASSEMBLY
209
210    /**
211     * Base class for all Alpha static instructions.
212     */
213    class AlphaStaticInst : public StaticInst
214    {
215      protected:
216
217        /// Make AlphaISA register dependence tags directly visible in
218        /// this class and derived classes.  Maybe these should really
219        /// live here and not in the AlphaISA namespace.
220        enum DependenceTags {
221            FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
222        };
223
224        /// Constructor.
225        AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
226                        OpClass __opClass)
227            : StaticInst(mnem, _machInst, __opClass)
228        {
229        }
230
231        /// Print a register name for disassembly given the unique
232        /// dependence tag number (FP or int).
233        void printReg(std::ostream &os, int reg) const;
234
235        std::string
236        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
237
238        void
239        advancePC(AlphaISA::PCState &pcState) const
240        {
241            pcState.advance();
242        }
243    };
244}};
245
246output decoder {{
247    void
248    AlphaStaticInst::printReg(std::ostream &os, int reg) const
249    {
250        if (reg < FP_Base_DepTag) {
251            ccprintf(os, "r%d", reg);
252        }
253        else {
254            ccprintf(os, "f%d", reg - FP_Base_DepTag);
255        }
256    }
257
258    std::string
259    AlphaStaticInst::generateDisassembly(Addr pc,
260                                         const SymbolTable *symtab) const
261    {
262        std::stringstream ss;
263
264        ccprintf(ss, "%-10s ", mnemonic);
265
266        // just print the first two source regs... if there's
267        // a third one, it's a read-modify-write dest (Rc),
268        // e.g. for CMOVxx
269        if (_numSrcRegs > 0) {
270            printReg(ss, _srcRegIdx[0]);
271        }
272        if (_numSrcRegs > 1) {
273            ss << ",";
274            printReg(ss, _srcRegIdx[1]);
275        }
276
277        // just print the first dest... if there's a second one,
278        // it's generally implicit
279        if (_numDestRegs > 0) {
280            if (_numSrcRegs > 0)
281                ss << ",";
282            printReg(ss, _destRegIdx[0]);
283        }
284
285        return ss.str();
286    }
287}};
288
289// Declarations for execute() methods.
290def template BasicExecDeclare {{
291    Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
292}};
293
294// Basic instruction class declaration template.
295def template BasicDeclare {{
296    /**
297     * Static instruction class for "%(mnemonic)s".
298     */
299    class %(class_name)s : public %(base_class)s
300    {
301      public:
302        /// Constructor.
303        %(class_name)s(ExtMachInst machInst);
304
305        %(BasicExecDeclare)s
306    };
307}};
308
309// Basic instruction class constructor template.
310def template BasicConstructor {{
311    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
312         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
313    {
314        %(constructor)s;
315    }
316}};
317
318// Basic instruction class execute method template.
319def template BasicExecute {{
320    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
321                                  Trace::InstRecord *traceData) const
322    {
323        Fault fault = NoFault;
324
325        %(fp_enable_check)s;
326        %(op_decl)s;
327        %(op_rd)s;
328        %(code)s;
329
330        if (fault == NoFault) {
331            %(op_wb)s;
332        }
333
334        return fault;
335    }
336}};
337
338// Basic decode template.
339def template BasicDecode {{
340    return new %(class_name)s(machInst);
341}};
342
343// Basic decode template, passing mnemonic in as string arg to constructor.
344def template BasicDecodeWithMnemonic {{
345    return new %(class_name)s("%(mnemonic)s", machInst);
346}};
347
348// The most basic instruction format... used only for a few misc. insts
349def format BasicOperate(code, *flags) {{
350    iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
351    header_output = BasicDeclare.subst(iop)
352    decoder_output = BasicConstructor.subst(iop)
353    decode_block = BasicDecode.subst(iop)
354    exec_output = BasicExecute.subst(iop)
355}};
356
357
358
359////////////////////////////////////////////////////////////////////
360//
361// Nop
362//
363
364output header {{
365    /**
366     * Static instruction class for no-ops.  This is a leaf class.
367     */
368    class Nop : public AlphaStaticInst
369    {
370        /// Disassembly of original instruction.
371        const std::string originalDisassembly;
372
373      public:
374        /// Constructor
375        Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
376            : AlphaStaticInst("nop", _machInst, No_OpClass),
377              originalDisassembly(_originalDisassembly)
378        {
379            flags[IsNop] = true;
380        }
381
382        ~Nop() { }
383
384        std::string
385        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
386
387        %(BasicExecDeclare)s
388    };
389
390    /// Helper function for decoding nops.  Substitute Nop object
391    /// for original inst passed in as arg (and delete latter).
392    static inline
393    AlphaStaticInst *
394    makeNop(AlphaStaticInst *inst)
395    {
396        AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
397        delete inst;
398        return nop;
399    }
400}};
401
402output decoder {{
403    std::string Nop::generateDisassembly(Addr pc,
404                                         const SymbolTable *symtab) const
405    {
406#ifdef SS_COMPATIBLE_DISASSEMBLY
407        return originalDisassembly;
408#else
409        return csprintf("%-10s (%s)", "nop", originalDisassembly);
410#endif
411    }
412}};
413
414output exec {{
415    Fault
416    Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
417    {
418        return NoFault;
419    }
420}};
421
422// integer & FP operate instructions use Rc as dest, so check for
423// Rc == 31 to detect nops
424def template OperateNopCheckDecode {{
425 {
426     AlphaStaticInst *i = new %(class_name)s(machInst);
427     if (RC == 31) {
428         i = makeNop(i);
429     }
430     return i;
431 }
432}};
433
434// Like BasicOperate format, but generates NOP if RC/FC == 31
435def format BasicOperateWithNopCheck(code, *opt_args) {{
436    iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
437    header_output = BasicDeclare.subst(iop)
438    decoder_output = BasicConstructor.subst(iop)
439    decode_block = OperateNopCheckDecode.subst(iop)
440    exec_output = BasicExecute.subst(iop)
441}};
442
443// Integer instruction templates, formats, etc.
444##include "int.isa"
445
446// Floating-point instruction templates, formats, etc.
447##include "fp.isa"
448
449// Memory instruction templates, formats, etc.
450##include "mem.isa"
451
452// Branch/jump instruction templates, formats, etc.
453##include "branch.isa"
454
455// PAL instruction templates, formats, etc.
456##include "pal.isa"
457
458// Opcdec fault instruction templates, formats, etc.
459##include "opcdec.isa"
460
461// Unimplemented instruction templates, formats, etc.
462##include "unimp.isa"
463
464// Unknown instruction templates, formats, etc.
465##include "unknown.isa"
466
467// Execution utility functions
468##include "util.isa"
469
470// The actual decoder
471##include "decoder.isa"
472