main.isa revision 5952:c1ee8282291d
1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2005 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// Alpha ISA description file. 34// 35//////////////////////////////////////////////////////////////////// 36 37 38//////////////////////////////////////////////////////////////////// 39// 40// Output include file directives. 41// 42 43output header {{ 44#include <sstream> 45#include <iostream> 46#include <iomanip> 47 48#include "arch/alpha/faults.hh" 49#include "config/ss_compatible_fp.hh" 50#include "cpu/static_inst.hh" 51#include "mem/request.hh" // some constructors use MemReq flags 52#include "mem/packet.hh" 53}}; 54 55output decoder {{ 56#include <cmath> 57 58#include "base/cprintf.hh" 59#include "base/fenv.hh" 60#include "base/loader/symtab.hh" 61#include "config/ss_compatible_fp.hh" 62#include "cpu/thread_context.hh" // for Jump::branchTarget() 63#include "mem/packet.hh" 64 65using namespace AlphaISA; 66}}; 67 68output exec {{ 69#include <math.h> 70 71#include "base/cp_annotate.hh" 72#include "sim/pseudo_inst.hh" 73#include "arch/alpha/ipr.hh" 74#include "base/fenv.hh" 75#include "config/ss_compatible_fp.hh" 76#include "cpu/base.hh" 77#include "cpu/exetrace.hh" 78#include "mem/packet.hh" 79#include "mem/packet_access.hh" 80#include "sim/sim_exit.hh" 81 82using namespace AlphaISA; 83}}; 84 85//////////////////////////////////////////////////////////////////// 86// 87// Namespace statement. Everything below this line will be in the 88// AlphaISAInst namespace. 89// 90 91 92namespace AlphaISA; 93 94//////////////////////////////////////////////////////////////////// 95// 96// Bitfield definitions. 97// 98 99// Universal (format-independent) fields 100def bitfield PALMODE <32:32>; 101def bitfield OPCODE <31:26>; 102def bitfield RA <25:21>; 103def bitfield RB <20:16>; 104 105// Memory format 106def signed bitfield MEMDISP <15: 0>; // displacement 107def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned) 108 109// Memory-format jumps 110def bitfield JMPFUNC <15:14>; // function code (disp<15:14>) 111def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>) 112 113// Branch format 114def signed bitfield BRDISP <20: 0>; // displacement 115 116// Integer operate format(s>; 117def bitfield INTIMM <20:13>; // integer immediate (literal) 118def bitfield IMM <12:12>; // immediate flag 119def bitfield INTFUNC <11: 5>; // function code 120def bitfield RC < 4: 0>; // dest reg 121 122// Floating-point operate format 123def bitfield FA <25:21>; 124def bitfield FB <20:16>; 125def bitfield FP_FULLFUNC <15: 5>; // complete function code 126 def bitfield FP_TRAPMODE <15:13>; // trapping mode 127 def bitfield FP_ROUNDMODE <12:11>; // rounding mode 128 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding 129 def bitfield FP_SRCTYPE <10: 9>; // source reg type 130 def bitfield FP_SHORTFUNC < 8: 5>; // short function code 131 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code 132def bitfield FC < 4: 0>; // dest reg 133 134// PALcode format 135def bitfield PALFUNC <25: 0>; // function code 136 137// EV5 PAL instructions: 138// HW_LD/HW_ST 139def bitfield HW_LDST_PHYS <15>; // address is physical 140def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR 141def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc 142def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b 143def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch 144def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked 145def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional 146def signed bitfield HW_LDST_DISP <9:0>; // signed displacement 147 148// HW_REI 149def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk 150def bitfield HW_REI_MBZ <13: 0>; // must be zero 151 152// HW_MTPR/MW_MFPR 153def bitfield HW_IPR_IDX <15:0>; // IPR index 154 155// M5 instructions 156def bitfield M5FUNC <7:0>; 157 158def operand_types {{ 159 'sb' : ('signed int', 8), 160 'ub' : ('unsigned int', 8), 161 'sw' : ('signed int', 16), 162 'uw' : ('unsigned int', 16), 163 'sl' : ('signed int', 32), 164 'ul' : ('unsigned int', 32), 165 'sq' : ('signed int', 64), 166 'uq' : ('unsigned int', 64), 167 'sf' : ('float', 32), 168 'df' : ('float', 64) 169}}; 170 171def operands {{ 172 # Int regs default to unsigned, but code should not count on this. 173 # For clarity, descriptions that depend on unsigned behavior should 174 # explicitly specify '.uq'. 175 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA', 176 'IsInteger', 1), 177 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB', 178 'IsInteger', 2), 179 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC', 180 'IsInteger', 3), 181 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), 182 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), 183 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 184 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 185 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), 186 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1), 187 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1), 188 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1), 189 # The next two are hacks for non-full-system call-pal emulation 190 'R0': ('IntReg', 'uq', '0', None, 1), 191 'R16': ('IntReg', 'uq', '16', None, 1), 192 'R17': ('IntReg', 'uq', '17', None, 1), 193 'R18': ('IntReg', 'uq', '18', None, 1) 194}}; 195 196//////////////////////////////////////////////////////////////////// 197// 198// Basic instruction classes/templates/formats etc. 199// 200 201output header {{ 202// uncomment the following to get SimpleScalar-compatible disassembly 203// (useful for diffing output traces). 204// #define SS_COMPATIBLE_DISASSEMBLY 205 206 /** 207 * Base class for all Alpha static instructions. 208 */ 209 class AlphaStaticInst : public StaticInst 210 { 211 protected: 212 213 /// Make AlphaISA register dependence tags directly visible in 214 /// this class and derived classes. Maybe these should really 215 /// live here and not in the AlphaISA namespace. 216 enum DependenceTags { 217 FP_Base_DepTag = AlphaISA::FP_Base_DepTag, 218 }; 219 220 /// Constructor. 221 AlphaStaticInst(const char *mnem, ExtMachInst _machInst, 222 OpClass __opClass) 223 : StaticInst(mnem, _machInst, __opClass) 224 { 225 } 226 227 /// Print a register name for disassembly given the unique 228 /// dependence tag number (FP or int). 229 void printReg(std::ostream &os, int reg) const; 230 231 std::string 232 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 233 }; 234}}; 235 236output decoder {{ 237 void 238 AlphaStaticInst::printReg(std::ostream &os, int reg) const 239 { 240 if (reg < FP_Base_DepTag) { 241 ccprintf(os, "r%d", reg); 242 } 243 else { 244 ccprintf(os, "f%d", reg - FP_Base_DepTag); 245 } 246 } 247 248 std::string 249 AlphaStaticInst::generateDisassembly(Addr pc, 250 const SymbolTable *symtab) const 251 { 252 std::stringstream ss; 253 254 ccprintf(ss, "%-10s ", mnemonic); 255 256 // just print the first two source regs... if there's 257 // a third one, it's a read-modify-write dest (Rc), 258 // e.g. for CMOVxx 259 if (_numSrcRegs > 0) { 260 printReg(ss, _srcRegIdx[0]); 261 } 262 if (_numSrcRegs > 1) { 263 ss << ","; 264 printReg(ss, _srcRegIdx[1]); 265 } 266 267 // just print the first dest... if there's a second one, 268 // it's generally implicit 269 if (_numDestRegs > 0) { 270 if (_numSrcRegs > 0) 271 ss << ","; 272 printReg(ss, _destRegIdx[0]); 273 } 274 275 return ss.str(); 276 } 277}}; 278 279// Declarations for execute() methods. 280def template BasicExecDeclare {{ 281 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; 282}}; 283 284// Basic instruction class declaration template. 285def template BasicDeclare {{ 286 /** 287 * Static instruction class for "%(mnemonic)s". 288 */ 289 class %(class_name)s : public %(base_class)s 290 { 291 public: 292 /// Constructor. 293 %(class_name)s(ExtMachInst machInst); 294 295 %(BasicExecDeclare)s 296 }; 297}}; 298 299// Basic instruction class constructor template. 300def template BasicConstructor {{ 301 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 302 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 303 { 304 %(constructor)s; 305 } 306}}; 307 308// Basic instruction class execute method template. 309def template BasicExecute {{ 310 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 311 Trace::InstRecord *traceData) const 312 { 313 Fault fault = NoFault; 314 315 %(fp_enable_check)s; 316 %(op_decl)s; 317 %(op_rd)s; 318 %(code)s; 319 320 if (fault == NoFault) { 321 %(op_wb)s; 322 } 323 324 return fault; 325 } 326}}; 327 328// Basic decode template. 329def template BasicDecode {{ 330 return new %(class_name)s(machInst); 331}}; 332 333// Basic decode template, passing mnemonic in as string arg to constructor. 334def template BasicDecodeWithMnemonic {{ 335 return new %(class_name)s("%(mnemonic)s", machInst); 336}}; 337 338// The most basic instruction format... used only for a few misc. insts 339def format BasicOperate(code, *flags) {{ 340 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags) 341 header_output = BasicDeclare.subst(iop) 342 decoder_output = BasicConstructor.subst(iop) 343 decode_block = BasicDecode.subst(iop) 344 exec_output = BasicExecute.subst(iop) 345}}; 346 347 348 349//////////////////////////////////////////////////////////////////// 350// 351// Nop 352// 353 354output header {{ 355 /** 356 * Static instruction class for no-ops. This is a leaf class. 357 */ 358 class Nop : public AlphaStaticInst 359 { 360 /// Disassembly of original instruction. 361 const std::string originalDisassembly; 362 363 public: 364 /// Constructor 365 Nop(const std::string _originalDisassembly, ExtMachInst _machInst) 366 : AlphaStaticInst("nop", _machInst, No_OpClass), 367 originalDisassembly(_originalDisassembly) 368 { 369 flags[IsNop] = true; 370 } 371 372 ~Nop() { } 373 374 std::string 375 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 376 377 %(BasicExecDeclare)s 378 }; 379 380 /// Helper function for decoding nops. Substitute Nop object 381 /// for original inst passed in as arg (and delete latter). 382 static inline 383 AlphaStaticInst * 384 makeNop(AlphaStaticInst *inst) 385 { 386 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst); 387 delete inst; 388 return nop; 389 } 390}}; 391 392output decoder {{ 393 std::string Nop::generateDisassembly(Addr pc, 394 const SymbolTable *symtab) const 395 { 396#ifdef SS_COMPATIBLE_DISASSEMBLY 397 return originalDisassembly; 398#else 399 return csprintf("%-10s (%s)", "nop", originalDisassembly); 400#endif 401 } 402}}; 403 404output exec {{ 405 Fault 406 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const 407 { 408 return NoFault; 409 } 410}}; 411 412// integer & FP operate instructions use Rc as dest, so check for 413// Rc == 31 to detect nops 414def template OperateNopCheckDecode {{ 415 { 416 AlphaStaticInst *i = new %(class_name)s(machInst); 417 if (RC == 31) { 418 i = makeNop(i); 419 } 420 return i; 421 } 422}}; 423 424// Like BasicOperate format, but generates NOP if RC/FC == 31 425def format BasicOperateWithNopCheck(code, *opt_args) {{ 426 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args) 427 header_output = BasicDeclare.subst(iop) 428 decoder_output = BasicConstructor.subst(iop) 429 decode_block = OperateNopCheckDecode.subst(iop) 430 exec_output = BasicExecute.subst(iop) 431}}; 432 433// Integer instruction templates, formats, etc. 434##include "int.isa" 435 436// Floating-point instruction templates, formats, etc. 437##include "fp.isa" 438 439// Memory instruction templates, formats, etc. 440##include "mem.isa" 441 442// Branch/jump instruction templates, formats, etc. 443##include "branch.isa" 444 445// PAL instruction templates, formats, etc. 446##include "pal.isa" 447 448// Opcdec fault instruction templates, formats, etc. 449##include "opcdec.isa" 450 451// Unimplemented instruction templates, formats, etc. 452##include "unimp.isa" 453 454// Unknown instruction templates, formats, etc. 455##include "unknown.isa" 456 457// Execution utility functions 458##include "util.isa" 459 460// The actual decoder 461##include "decoder.isa" 462