main.isa revision 3457:7479ebe49444 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// Alpha ISA description file.
34//
35////////////////////////////////////////////////////////////////////
36
37
38////////////////////////////////////////////////////////////////////
39//
40// Output include file directives.
41//
42
43output header {{
44#include <sstream>
45#include <iostream>
46#include <iomanip>
47
48#include "arch/alpha/faults.hh"
49#include "config/ss_compatible_fp.hh"
50#include "cpu/static_inst.hh"
51#include "mem/request.hh"  // some constructors use MemReq flags
52#include "mem/packet.hh"
53}};
54
55output decoder {{
56#include <cmath>
57
58#include "base/cprintf.hh"
59#include "base/fenv.hh"
60#include "base/loader/symtab.hh"
61#include "config/ss_compatible_fp.hh"
62#include "cpu/thread_context.hh"  // for Jump::branchTarget()
63#include "mem/packet.hh"
64
65using namespace AlphaISA;
66}};
67
68output exec {{
69#include <math.h>
70
71#if FULL_SYSTEM
72#include "sim/pseudo_inst.hh"
73#endif
74#include "arch/alpha/ipr.hh"
75#include "base/fenv.hh"
76#include "config/ss_compatible_fp.hh"
77#include "cpu/base.hh"
78#include "cpu/exetrace.hh"
79#include "mem/packet.hh"
80#include "mem/packet_access.hh"
81#include "sim/sim_exit.hh"
82
83using namespace AlphaISA;
84}};
85
86////////////////////////////////////////////////////////////////////
87//
88// Namespace statement.  Everything below this line will be in the
89// AlphaISAInst namespace.
90//
91
92
93namespace AlphaISA;
94
95////////////////////////////////////////////////////////////////////
96//
97// Bitfield definitions.
98//
99
100// Universal (format-independent) fields
101def bitfield PALMODE    <32:32>;
102def bitfield OPCODE	<31:26>;
103def bitfield RA		<25:21>;
104def bitfield RB		<20:16>;
105
106// Memory format
107def signed bitfield MEMDISP <15: 0>; // displacement
108def        bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
109
110// Memory-format jumps
111def bitfield JMPFUNC	<15:14>; // function code (disp<15:14>)
112def bitfield JMPHINT	<13: 0>; // tgt Icache idx hint (disp<13:0>)
113
114// Branch format
115def signed bitfield BRDISP <20: 0>; // displacement
116
117// Integer operate format(s>;
118def bitfield INTIMM	<20:13>; // integer immediate (literal)
119def bitfield IMM	<12:12>; // immediate flag
120def bitfield INTFUNC	<11: 5>; // function code
121def bitfield RC		< 4: 0>; // dest reg
122
123// Floating-point operate format
124def bitfield FA		  <25:21>;
125def bitfield FB		  <20:16>;
126def bitfield FP_FULLFUNC  <15: 5>; // complete function code
127    def bitfield FP_TRAPMODE  <15:13>; // trapping mode
128    def bitfield FP_ROUNDMODE <12:11>; // rounding mode
129    def bitfield FP_TYPEFUNC  <10: 5>; // type+func: handiest for decoding
130        def bitfield FP_SRCTYPE   <10: 9>; // source reg type
131        def bitfield FP_SHORTFUNC < 8: 5>; // short function code
132        def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
133def bitfield FC		  < 4: 0>; // dest reg
134
135// PALcode format
136def bitfield PALFUNC	<25: 0>; // function code
137
138// EV5 PAL instructions:
139// HW_LD/HW_ST
140def bitfield HW_LDST_PHYS  <15>; // address is physical
141def bitfield HW_LDST_ALT   <14>; // use ALT_MODE IPR
142def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
143def bitfield HW_LDST_QUAD  <12>; // size: 0=32b, 1=64b
144def bitfield HW_LDST_VPTE  <11>; // HW_LD only: is PTE fetch
145def bitfield HW_LDST_LOCK  <10>; // HW_LD only: is load locked
146def bitfield HW_LDST_COND  <10>; // HW_ST only: is store conditional
147def signed bitfield HW_LDST_DISP  <9:0>; // signed displacement
148
149// HW_REI
150def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
151def bitfield HW_REI_MBZ <13: 0>; // must be zero
152
153// HW_MTPR/MW_MFPR
154def bitfield HW_IPR_IDX <15:0>;	 // IPR index
155
156// M5 instructions
157def bitfield M5FUNC <7:0>;
158
159def operand_types {{
160    'sb' : ('signed int', 8),
161    'ub' : ('unsigned int', 8),
162    'sw' : ('signed int', 16),
163    'uw' : ('unsigned int', 16),
164    'sl' : ('signed int', 32),
165    'ul' : ('unsigned int', 32),
166    'sq' : ('signed int', 64),
167    'uq' : ('unsigned int', 64),
168    'sf' : ('float', 32),
169    'df' : ('float', 64)
170}};
171
172def operands {{
173    # Int regs default to unsigned, but code should not count on this.
174    # For clarity, descriptions that depend on unsigned behavior should
175    # explicitly specify '.uq'.
176    'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA',
177           'IsInteger', 1),
178    'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB',
179           'IsInteger', 2),
180    'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC',
181           'IsInteger', 3),
182    'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
183    'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
184    'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
185    'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
186    'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
187    'Runiq': ('ControlReg', 'uq', 'AlphaISA::Uniq_DepTag', None, 1),
188    'FPCR':  ('ControlReg', 'uq', 'AlphaISA::Fpcr_DepTag', None, 1),
189    'IntrFlag': ('ControlReg', 'uq', 'AlphaISA::Intr_Flag_DepTag', None, 1),
190    # The next two are hacks for non-full-system call-pal emulation
191    'R0':  ('IntReg', 'uq', '0', None, 1),
192    'R16': ('IntReg', 'uq', '16', None, 1),
193    'R17': ('IntReg', 'uq', '17', None, 1),
194    'R18': ('IntReg', 'uq', '18', None, 1)
195}};
196
197////////////////////////////////////////////////////////////////////
198//
199// Basic instruction classes/templates/formats etc.
200//
201
202output header {{
203// uncomment the following to get SimpleScalar-compatible disassembly
204// (useful for diffing output traces).
205// #define SS_COMPATIBLE_DISASSEMBLY
206
207    /**
208     * Base class for all Alpha static instructions.
209     */
210    class AlphaStaticInst : public StaticInst
211    {
212      protected:
213
214        /// Make AlphaISA register dependence tags directly visible in
215        /// this class and derived classes.  Maybe these should really
216        /// live here and not in the AlphaISA namespace.
217        enum DependenceTags {
218            FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
219            Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
220            Uniq_DepTag = AlphaISA::Uniq_DepTag,
221            Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
222            Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
223            IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
224        };
225
226        /// Constructor.
227        AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
228                        OpClass __opClass)
229            : StaticInst(mnem, _machInst, __opClass)
230        {
231        }
232
233        /// Print a register name for disassembly given the unique
234        /// dependence tag number (FP or int).
235        void printReg(std::ostream &os, int reg) const;
236
237        std::string
238        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
239    };
240}};
241
242output decoder {{
243    void
244    AlphaStaticInst::printReg(std::ostream &os, int reg) const
245    {
246        if (reg < FP_Base_DepTag) {
247            ccprintf(os, "r%d", reg);
248        }
249        else {
250            ccprintf(os, "f%d", reg - FP_Base_DepTag);
251        }
252    }
253
254    std::string
255    AlphaStaticInst::generateDisassembly(Addr pc,
256                                         const SymbolTable *symtab) const
257    {
258        std::stringstream ss;
259
260        ccprintf(ss, "%-10s ", mnemonic);
261
262        // just print the first two source regs... if there's
263        // a third one, it's a read-modify-write dest (Rc),
264        // e.g. for CMOVxx
265        if (_numSrcRegs > 0) {
266            printReg(ss, _srcRegIdx[0]);
267        }
268        if (_numSrcRegs > 1) {
269            ss << ",";
270            printReg(ss, _srcRegIdx[1]);
271        }
272
273        // just print the first dest... if there's a second one,
274        // it's generally implicit
275        if (_numDestRegs > 0) {
276            if (_numSrcRegs > 0)
277                ss << ",";
278            printReg(ss, _destRegIdx[0]);
279        }
280
281        return ss.str();
282    }
283}};
284
285// Declarations for execute() methods.
286def template BasicExecDeclare {{
287    Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
288}};
289
290// Basic instruction class declaration template.
291def template BasicDeclare {{
292    /**
293     * Static instruction class for "%(mnemonic)s".
294     */
295    class %(class_name)s : public %(base_class)s
296    {
297      public:
298        /// Constructor.
299        %(class_name)s(ExtMachInst machInst);
300
301        %(BasicExecDeclare)s
302    };
303}};
304
305// Basic instruction class constructor template.
306def template BasicConstructor {{
307    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
308         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
309    {
310        %(constructor)s;
311    }
312}};
313
314// Basic instruction class execute method template.
315def template BasicExecute {{
316    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
317                                  Trace::InstRecord *traceData) const
318    {
319        Fault fault = NoFault;
320
321        %(fp_enable_check)s;
322        %(op_decl)s;
323        %(op_rd)s;
324        %(code)s;
325
326        if (fault == NoFault) {
327            %(op_wb)s;
328        }
329
330        return fault;
331    }
332}};
333
334// Basic decode template.
335def template BasicDecode {{
336    return new %(class_name)s(machInst);
337}};
338
339// Basic decode template, passing mnemonic in as string arg to constructor.
340def template BasicDecodeWithMnemonic {{
341    return new %(class_name)s("%(mnemonic)s", machInst);
342}};
343
344// The most basic instruction format... used only for a few misc. insts
345def format BasicOperate(code, *flags) {{
346    iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
347    header_output = BasicDeclare.subst(iop)
348    decoder_output = BasicConstructor.subst(iop)
349    decode_block = BasicDecode.subst(iop)
350    exec_output = BasicExecute.subst(iop)
351}};
352
353
354
355////////////////////////////////////////////////////////////////////
356//
357// Nop
358//
359
360output header {{
361    /**
362     * Static instruction class for no-ops.  This is a leaf class.
363     */
364    class Nop : public AlphaStaticInst
365    {
366        /// Disassembly of original instruction.
367        const std::string originalDisassembly;
368
369      public:
370        /// Constructor
371        Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
372            : AlphaStaticInst("nop", _machInst, No_OpClass),
373              originalDisassembly(_originalDisassembly)
374        {
375            flags[IsNop] = true;
376        }
377
378        ~Nop() { }
379
380        std::string
381        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
382
383        %(BasicExecDeclare)s
384    };
385
386    /// Helper function for decoding nops.  Substitute Nop object
387    /// for original inst passed in as arg (and delete latter).
388    static inline
389    AlphaStaticInst *
390    makeNop(AlphaStaticInst *inst)
391    {
392        AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
393        delete inst;
394        return nop;
395    }
396}};
397
398output decoder {{
399    std::string Nop::generateDisassembly(Addr pc,
400                                         const SymbolTable *symtab) const
401    {
402#ifdef SS_COMPATIBLE_DISASSEMBLY
403        return originalDisassembly;
404#else
405        return csprintf("%-10s (%s)", "nop", originalDisassembly);
406#endif
407    }
408}};
409
410output exec {{
411    Fault
412    Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
413    {
414        return NoFault;
415    }
416}};
417
418// integer & FP operate instructions use Rc as dest, so check for
419// Rc == 31 to detect nops
420def template OperateNopCheckDecode {{
421 {
422     AlphaStaticInst *i = new %(class_name)s(machInst);
423     if (RC == 31) {
424         i = makeNop(i);
425     }
426     return i;
427 }
428}};
429
430// Like BasicOperate format, but generates NOP if RC/FC == 31
431def format BasicOperateWithNopCheck(code, *opt_args) {{
432    iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
433                        opt_args)
434    header_output = BasicDeclare.subst(iop)
435    decoder_output = BasicConstructor.subst(iop)
436    decode_block = OperateNopCheckDecode.subst(iop)
437    exec_output = BasicExecute.subst(iop)
438}};
439
440// Integer instruction templates, formats, etc.
441##include "int.isa"
442
443// Floating-point instruction templates, formats, etc.
444##include "fp.isa"
445
446// Memory instruction templates, formats, etc.
447##include "mem.isa"
448
449// Branch/jump instruction templates, formats, etc.
450##include "branch.isa"
451
452// PAL instruction templates, formats, etc.
453##include "pal.isa"
454
455// Opcdec fault instruction templates, formats, etc.
456##include "opcdec.isa"
457
458// Unimplemented instruction templates, formats, etc.
459##include "unimp.isa"
460
461// Unknown instruction templates, formats, etc.
462##include "unknown.isa"
463
464// Execution utility functions
465##include "util.isa"
466
467// The actual decoder
468##include "decoder.isa"
469