main.isa revision 3349:fec4a86fa212 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// Alpha ISA description file.
34//
35////////////////////////////////////////////////////////////////////
36
37
38////////////////////////////////////////////////////////////////////
39//
40// Output include file directives.
41//
42
43output header {{
44#include <sstream>
45#include <iostream>
46#include <iomanip>
47
48#include "arch/alpha/faults.hh"
49#include "config/ss_compatible_fp.hh"
50#include "cpu/static_inst.hh"
51#include "mem/request.hh"  // some constructors use MemReq flags
52#include "mem/packet.hh"
53}};
54
55output decoder {{
56#include <cmath>
57
58#include "base/cprintf.hh"
59#include "base/fenv.hh"
60#include "base/loader/symtab.hh"
61#include "config/ss_compatible_fp.hh"
62#include "cpu/thread_context.hh"  // for Jump::branchTarget()
63#include "mem/packet.hh"
64
65using namespace AlphaISA;
66}};
67
68output exec {{
69#include <math.h>
70
71#if FULL_SYSTEM
72#include "sim/pseudo_inst.hh"
73#endif
74#include "base/fenv.hh"
75#include "config/ss_compatible_fp.hh"
76#include "cpu/base.hh"
77#include "cpu/exetrace.hh"
78#include "mem/packet.hh"
79#include "mem/packet_access.hh"
80#include "sim/sim_exit.hh"
81
82using namespace AlphaISA;
83}};
84
85////////////////////////////////////////////////////////////////////
86//
87// Namespace statement.  Everything below this line will be in the
88// AlphaISAInst namespace.
89//
90
91
92namespace AlphaISA;
93
94////////////////////////////////////////////////////////////////////
95//
96// Bitfield definitions.
97//
98
99// Universal (format-independent) fields
100def bitfield PALMODE    <32:32>;
101def bitfield OPCODE	<31:26>;
102def bitfield RA		<25:21>;
103def bitfield RB		<20:16>;
104
105// Memory format
106def signed bitfield MEMDISP <15: 0>; // displacement
107def        bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
108
109// Memory-format jumps
110def bitfield JMPFUNC	<15:14>; // function code (disp<15:14>)
111def bitfield JMPHINT	<13: 0>; // tgt Icache idx hint (disp<13:0>)
112
113// Branch format
114def signed bitfield BRDISP <20: 0>; // displacement
115
116// Integer operate format(s>;
117def bitfield INTIMM	<20:13>; // integer immediate (literal)
118def bitfield IMM	<12:12>; // immediate flag
119def bitfield INTFUNC	<11: 5>; // function code
120def bitfield RC		< 4: 0>; // dest reg
121
122// Floating-point operate format
123def bitfield FA		  <25:21>;
124def bitfield FB		  <20:16>;
125def bitfield FP_FULLFUNC  <15: 5>; // complete function code
126    def bitfield FP_TRAPMODE  <15:13>; // trapping mode
127    def bitfield FP_ROUNDMODE <12:11>; // rounding mode
128    def bitfield FP_TYPEFUNC  <10: 5>; // type+func: handiest for decoding
129        def bitfield FP_SRCTYPE   <10: 9>; // source reg type
130        def bitfield FP_SHORTFUNC < 8: 5>; // short function code
131        def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
132def bitfield FC		  < 4: 0>; // dest reg
133
134// PALcode format
135def bitfield PALFUNC	<25: 0>; // function code
136
137// EV5 PAL instructions:
138// HW_LD/HW_ST
139def bitfield HW_LDST_PHYS  <15>; // address is physical
140def bitfield HW_LDST_ALT   <14>; // use ALT_MODE IPR
141def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
142def bitfield HW_LDST_QUAD  <12>; // size: 0=32b, 1=64b
143def bitfield HW_LDST_VPTE  <11>; // HW_LD only: is PTE fetch
144def bitfield HW_LDST_LOCK  <10>; // HW_LD only: is load locked
145def bitfield HW_LDST_COND  <10>; // HW_ST only: is store conditional
146def signed bitfield HW_LDST_DISP  <9:0>; // signed displacement
147
148// HW_REI
149def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
150def bitfield HW_REI_MBZ <13: 0>; // must be zero
151
152// HW_MTPR/MW_MFPR
153def bitfield HW_IPR_IDX <15:0>;	 // IPR index
154
155// M5 instructions
156def bitfield M5FUNC <7:0>;
157
158def operand_types {{
159    'sb' : ('signed int', 8),
160    'ub' : ('unsigned int', 8),
161    'sw' : ('signed int', 16),
162    'uw' : ('unsigned int', 16),
163    'sl' : ('signed int', 32),
164    'ul' : ('unsigned int', 32),
165    'sq' : ('signed int', 64),
166    'uq' : ('unsigned int', 64),
167    'sf' : ('float', 32),
168    'df' : ('float', 64)
169}};
170
171def operands {{
172    # Int regs default to unsigned, but code should not count on this.
173    # For clarity, descriptions that depend on unsigned behavior should
174    # explicitly specify '.uq'.
175    'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA',
176           'IsInteger', 1),
177    'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB',
178           'IsInteger', 2),
179    'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC',
180           'IsInteger', 3),
181    'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
182    'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
183    'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
184    'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
185    'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
186    'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
187    'FPCR':  (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
188    # The next two are hacks for non-full-system call-pal emulation
189    'R0':  ('IntReg', 'uq', '0', None, 1),
190    'R16': ('IntReg', 'uq', '16', None, 1),
191    'R17': ('IntReg', 'uq', '17', None, 1),
192    'R18': ('IntReg', 'uq', '18', None, 1)
193}};
194
195////////////////////////////////////////////////////////////////////
196//
197// Basic instruction classes/templates/formats etc.
198//
199
200output header {{
201// uncomment the following to get SimpleScalar-compatible disassembly
202// (useful for diffing output traces).
203// #define SS_COMPATIBLE_DISASSEMBLY
204
205    /**
206     * Base class for all Alpha static instructions.
207     */
208    class AlphaStaticInst : public StaticInst
209    {
210      protected:
211
212        /// Make AlphaISA register dependence tags directly visible in
213        /// this class and derived classes.  Maybe these should really
214        /// live here and not in the AlphaISA namespace.
215        enum DependenceTags {
216            FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
217            Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
218            Uniq_DepTag = AlphaISA::Uniq_DepTag,
219            Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
220            Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
221            IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
222        };
223
224        /// Constructor.
225        AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
226                        OpClass __opClass)
227            : StaticInst(mnem, _machInst, __opClass)
228        {
229        }
230
231        /// Print a register name for disassembly given the unique
232        /// dependence tag number (FP or int).
233        void printReg(std::ostream &os, int reg) const;
234
235        std::string
236        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
237    };
238}};
239
240output decoder {{
241    void
242    AlphaStaticInst::printReg(std::ostream &os, int reg) const
243    {
244        if (reg < FP_Base_DepTag) {
245            ccprintf(os, "r%d", reg);
246        }
247        else {
248            ccprintf(os, "f%d", reg - FP_Base_DepTag);
249        }
250    }
251
252    std::string
253    AlphaStaticInst::generateDisassembly(Addr pc,
254                                         const SymbolTable *symtab) const
255    {
256        std::stringstream ss;
257
258        ccprintf(ss, "%-10s ", mnemonic);
259
260        // just print the first two source regs... if there's
261        // a third one, it's a read-modify-write dest (Rc),
262        // e.g. for CMOVxx
263        if (_numSrcRegs > 0) {
264            printReg(ss, _srcRegIdx[0]);
265        }
266        if (_numSrcRegs > 1) {
267            ss << ",";
268            printReg(ss, _srcRegIdx[1]);
269        }
270
271        // just print the first dest... if there's a second one,
272        // it's generally implicit
273        if (_numDestRegs > 0) {
274            if (_numSrcRegs > 0)
275                ss << ",";
276            printReg(ss, _destRegIdx[0]);
277        }
278
279        return ss.str();
280    }
281}};
282
283// Declarations for execute() methods.
284def template BasicExecDeclare {{
285    Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
286}};
287
288// Basic instruction class declaration template.
289def template BasicDeclare {{
290    /**
291     * Static instruction class for "%(mnemonic)s".
292     */
293    class %(class_name)s : public %(base_class)s
294    {
295      public:
296        /// Constructor.
297        %(class_name)s(ExtMachInst machInst);
298
299        %(BasicExecDeclare)s
300    };
301}};
302
303// Basic instruction class constructor template.
304def template BasicConstructor {{
305    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
306         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
307    {
308        %(constructor)s;
309    }
310}};
311
312// Basic instruction class execute method template.
313def template BasicExecute {{
314    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
315                                  Trace::InstRecord *traceData) const
316    {
317        Fault fault = NoFault;
318
319        %(fp_enable_check)s;
320        %(op_decl)s;
321        %(op_rd)s;
322        %(code)s;
323
324        if (fault == NoFault) {
325            %(op_wb)s;
326        }
327
328        return fault;
329    }
330}};
331
332// Basic decode template.
333def template BasicDecode {{
334    return new %(class_name)s(machInst);
335}};
336
337// Basic decode template, passing mnemonic in as string arg to constructor.
338def template BasicDecodeWithMnemonic {{
339    return new %(class_name)s("%(mnemonic)s", machInst);
340}};
341
342// The most basic instruction format... used only for a few misc. insts
343def format BasicOperate(code, *flags) {{
344    iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
345    header_output = BasicDeclare.subst(iop)
346    decoder_output = BasicConstructor.subst(iop)
347    decode_block = BasicDecode.subst(iop)
348    exec_output = BasicExecute.subst(iop)
349}};
350
351
352
353////////////////////////////////////////////////////////////////////
354//
355// Nop
356//
357
358output header {{
359    /**
360     * Static instruction class for no-ops.  This is a leaf class.
361     */
362    class Nop : public AlphaStaticInst
363    {
364        /// Disassembly of original instruction.
365        const std::string originalDisassembly;
366
367      public:
368        /// Constructor
369        Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
370            : AlphaStaticInst("nop", _machInst, No_OpClass),
371              originalDisassembly(_originalDisassembly)
372        {
373            flags[IsNop] = true;
374        }
375
376        ~Nop() { }
377
378        std::string
379        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
380
381        %(BasicExecDeclare)s
382    };
383
384    /// Helper function for decoding nops.  Substitute Nop object
385    /// for original inst passed in as arg (and delete latter).
386    static inline
387    AlphaStaticInst *
388    makeNop(AlphaStaticInst *inst)
389    {
390        AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
391        delete inst;
392        return nop;
393    }
394}};
395
396output decoder {{
397    std::string Nop::generateDisassembly(Addr pc,
398                                         const SymbolTable *symtab) const
399    {
400#ifdef SS_COMPATIBLE_DISASSEMBLY
401        return originalDisassembly;
402#else
403        return csprintf("%-10s (%s)", "nop", originalDisassembly);
404#endif
405    }
406}};
407
408output exec {{
409    Fault
410    Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
411    {
412        return NoFault;
413    }
414}};
415
416// integer & FP operate instructions use Rc as dest, so check for
417// Rc == 31 to detect nops
418def template OperateNopCheckDecode {{
419 {
420     AlphaStaticInst *i = new %(class_name)s(machInst);
421     if (RC == 31) {
422         i = makeNop(i);
423     }
424     return i;
425 }
426}};
427
428// Like BasicOperate format, but generates NOP if RC/FC == 31
429def format BasicOperateWithNopCheck(code, *opt_args) {{
430    iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
431                        opt_args)
432    header_output = BasicDeclare.subst(iop)
433    decoder_output = BasicConstructor.subst(iop)
434    decode_block = OperateNopCheckDecode.subst(iop)
435    exec_output = BasicExecute.subst(iop)
436}};
437
438// Integer instruction templates, formats, etc.
439##include "int.isa"
440
441// Floating-point instruction templates, formats, etc.
442##include "fp.isa"
443
444// Memory instruction templates, formats, etc.
445##include "mem.isa"
446
447// Branch/jump instruction templates, formats, etc.
448##include "branch.isa"
449
450// PAL instruction templates, formats, etc.
451##include "pal.isa"
452
453// Opcdec fault instruction templates, formats, etc.
454##include "opcdec.isa"
455
456// Unimplemented instruction templates, formats, etc.
457##include "unimp.isa"
458
459// Unknown instruction templates, formats, etc.
460##include "unknown.isa"
461
462// Execution utility functions
463##include "util.isa"
464
465// The actual decoder
466##include "decoder.isa"
467