main.isa revision 3348:11f6ef023158
112798Snikos.nikoleris@arm.com// -*- mode:c++ -*- 212798Snikos.nikoleris@arm.com 312798Snikos.nikoleris@arm.com// Copyright (c) 2003-2005 The Regents of The University of Michigan 412798Snikos.nikoleris@arm.com// All rights reserved. 512798Snikos.nikoleris@arm.com// 612798Snikos.nikoleris@arm.com// Redistribution and use in source and binary forms, with or without 712798Snikos.nikoleris@arm.com// modification, are permitted provided that the following conditions are 812798Snikos.nikoleris@arm.com// met: redistributions of source code must retain the above copyright 912798Snikos.nikoleris@arm.com// notice, this list of conditions and the following disclaimer; 1012798Snikos.nikoleris@arm.com// redistributions in binary form must reproduce the above copyright 1112798Snikos.nikoleris@arm.com// notice, this list of conditions and the following disclaimer in the 1212798Snikos.nikoleris@arm.com// documentation and/or other materials provided with the distribution; 133101Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 143101Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 153101Sstever@eecs.umich.edu// this software without specific prior written permission. 163101Sstever@eecs.umich.edu// 173101Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 183101Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 193101Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 203101Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 213101Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 223101Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 233101Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 243101Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 253101Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 263101Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 273101Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 283101Sstever@eecs.umich.edu// 293101Sstever@eecs.umich.edu// Authors: Steve Reinhardt 303101Sstever@eecs.umich.edu 313101Sstever@eecs.umich.edu//////////////////////////////////////////////////////////////////// 323101Sstever@eecs.umich.edu// 333101Sstever@eecs.umich.edu// Alpha ISA description file. 343101Sstever@eecs.umich.edu// 353101Sstever@eecs.umich.edu//////////////////////////////////////////////////////////////////// 363101Sstever@eecs.umich.edu 373101Sstever@eecs.umich.edu 383101Sstever@eecs.umich.edu//////////////////////////////////////////////////////////////////// 393101Sstever@eecs.umich.edu// 403101Sstever@eecs.umich.edu// Output include file directives. 413101Sstever@eecs.umich.edu// 423101Sstever@eecs.umich.edu 433101Sstever@eecs.umich.eduoutput header {{ 443101Sstever@eecs.umich.edu#include <sstream> 453101Sstever@eecs.umich.edu#include <iostream> 463101Sstever@eecs.umich.edu#include <iomanip> 473101Sstever@eecs.umich.edu 4813714Sandreas.sandberg@arm.com#include "config/ss_compatible_fp.hh" 4913714Sandreas.sandberg@arm.com#include "cpu/static_inst.hh" 5013719Sandreas.sandberg@arm.com#include "arch/alpha/faults.hh" 5113719Sandreas.sandberg@arm.com#include "mem/request.hh" // some constructors use MemReq flags 5213719Sandreas.sandberg@arm.com}}; 5313714Sandreas.sandberg@arm.com 543179Sstever@eecs.umich.eduoutput decoder {{ 553179Sstever@eecs.umich.edu#include "base/cprintf.hh" 5612798Snikos.nikoleris@arm.com#include "base/fenv.hh" 573101Sstever@eecs.umich.edu#include "base/loader/symtab.hh" 583101Sstever@eecs.umich.edu#include "config/ss_compatible_fp.hh" 593101Sstever@eecs.umich.edu#include "cpu/thread_context.hh" // for Jump::branchTarget() 603101Sstever@eecs.umich.edu 6112798Snikos.nikoleris@arm.com#include <math.h> 623101Sstever@eecs.umich.edu 633109Sstever@eecs.umich.eduusing namespace AlphaISA; 643109Sstever@eecs.umich.edu}}; 653109Sstever@eecs.umich.edu 663109Sstever@eecs.umich.eduoutput exec {{ 673109Sstever@eecs.umich.edu#include <math.h> 683109Sstever@eecs.umich.edu 693109Sstever@eecs.umich.edu#if FULL_SYSTEM 703109Sstever@eecs.umich.edu#include "sim/pseudo_inst.hh" 713109Sstever@eecs.umich.edu#endif 723101Sstever@eecs.umich.edu#include "base/fenv.hh" 733101Sstever@eecs.umich.edu#include "config/ss_compatible_fp.hh" 7413663Sandreas.sandberg@arm.com#include "cpu/base.hh" 7513663Sandreas.sandberg@arm.com#include "cpu/exetrace.hh" 763101Sstever@eecs.umich.edu#include "mem/packet.hh" 773101Sstever@eecs.umich.edu#include "mem/packet_access.hh" 7812798Snikos.nikoleris@arm.com#include "sim/sim_exit.hh" 7912798Snikos.nikoleris@arm.com 803101Sstever@eecs.umich.eduusing namespace AlphaISA; 8112798Snikos.nikoleris@arm.com}}; 8213663Sandreas.sandberg@arm.com 8313663Sandreas.sandberg@arm.com//////////////////////////////////////////////////////////////////// 8412798Snikos.nikoleris@arm.com// 853101Sstever@eecs.umich.edu// Namespace statement. Everything below this line will be in the 863101Sstever@eecs.umich.edu// AlphaISAInst namespace. 873101Sstever@eecs.umich.edu// 883101Sstever@eecs.umich.edu 8912798Snikos.nikoleris@arm.com 9012798Snikos.nikoleris@arm.comnamespace AlphaISA; 9112798Snikos.nikoleris@arm.com 9212798Snikos.nikoleris@arm.com//////////////////////////////////////////////////////////////////// 9312798Snikos.nikoleris@arm.com// 9412798Snikos.nikoleris@arm.com// Bitfield definitions. 9512798Snikos.nikoleris@arm.com// 9613663Sandreas.sandberg@arm.com 9713663Sandreas.sandberg@arm.com// Universal (format-independent) fields 9812798Snikos.nikoleris@arm.comdef bitfield PALMODE <32:32>; 9912798Snikos.nikoleris@arm.comdef bitfield OPCODE <31:26>; 10012798Snikos.nikoleris@arm.comdef bitfield RA <25:21>; 1013101Sstever@eecs.umich.edudef bitfield RB <20:16>; 1023101Sstever@eecs.umich.edu 1033101Sstever@eecs.umich.edu// Memory format 1043101Sstever@eecs.umich.edudef signed bitfield MEMDISP <15: 0>; // displacement 1053101Sstever@eecs.umich.edudef bitfield MEMFUNC <15: 0>; // function code (same field, unsigned) 1063101Sstever@eecs.umich.edu 1073101Sstever@eecs.umich.edu// Memory-format jumps 1083101Sstever@eecs.umich.edudef bitfield JMPFUNC <15:14>; // function code (disp<15:14>) 1093101Sstever@eecs.umich.edudef bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>) 11010195SGeoffrey.Blake@arm.com 11110195SGeoffrey.Blake@arm.com// Branch format 11210195SGeoffrey.Blake@arm.comdef signed bitfield BRDISP <20: 0>; // displacement 11310195SGeoffrey.Blake@arm.com 1143101Sstever@eecs.umich.edu// Integer operate format(s>; 1153101Sstever@eecs.umich.edudef bitfield INTIMM <20:13>; // integer immediate (literal) 1163101Sstever@eecs.umich.edudef bitfield IMM <12:12>; // immediate flag 1173101Sstever@eecs.umich.edudef bitfield INTFUNC <11: 5>; // function code 1183101Sstever@eecs.umich.edudef bitfield RC < 4: 0>; // dest reg 1193101Sstever@eecs.umich.edu 12010195SGeoffrey.Blake@arm.com// Floating-point operate format 12110195SGeoffrey.Blake@arm.comdef bitfield FA <25:21>; 12210195SGeoffrey.Blake@arm.comdef bitfield FB <20:16>; 1233101Sstever@eecs.umich.edudef bitfield FP_FULLFUNC <15: 5>; // complete function code 12413663Sandreas.sandberg@arm.com def bitfield FP_TRAPMODE <15:13>; // trapping mode 12513663Sandreas.sandberg@arm.com def bitfield FP_ROUNDMODE <12:11>; // rounding mode 12613663Sandreas.sandberg@arm.com def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding 1273101Sstever@eecs.umich.edu def bitfield FP_SRCTYPE <10: 9>; // source reg type 1283101Sstever@eecs.umich.edu def bitfield FP_SHORTFUNC < 8: 5>; // short function code 1293101Sstever@eecs.umich.edu def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code 13013663Sandreas.sandberg@arm.comdef bitfield FC < 4: 0>; // dest reg 1313101Sstever@eecs.umich.edu 1323101Sstever@eecs.umich.edu// PALcode format 13312798Snikos.nikoleris@arm.comdef bitfield PALFUNC <25: 0>; // function code 1343101Sstever@eecs.umich.edu 1353101Sstever@eecs.umich.edu// EV5 PAL instructions: 1363101Sstever@eecs.umich.edu// HW_LD/HW_ST 1373101Sstever@eecs.umich.edudef bitfield HW_LDST_PHYS <15>; // address is physical 1383101Sstever@eecs.umich.edudef bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR 1393101Sstever@eecs.umich.edudef bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc 1403101Sstever@eecs.umich.edudef bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b 1413101Sstever@eecs.umich.edudef bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch 1423101Sstever@eecs.umich.edudef bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked 1433101Sstever@eecs.umich.edudef bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional 1443101Sstever@eecs.umich.edudef signed bitfield HW_LDST_DISP <9:0>; // signed displacement 1453101Sstever@eecs.umich.edu 1463101Sstever@eecs.umich.edu// HW_REI 1473101Sstever@eecs.umich.edudef bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk 1483109Sstever@eecs.umich.edudef bitfield HW_REI_MBZ <13: 0>; // must be zero 1493109Sstever@eecs.umich.edu 1503109Sstever@eecs.umich.edu// HW_MTPR/MW_MFPR 1513101Sstever@eecs.umich.edudef bitfield HW_IPR_IDX <15:0>; // IPR index 1523101Sstever@eecs.umich.edu 1533101Sstever@eecs.umich.edu// M5 instructions 1543101Sstever@eecs.umich.edudef bitfield M5FUNC <7:0>; 1553101Sstever@eecs.umich.edu 1563101Sstever@eecs.umich.edudef operand_types {{ 1573101Sstever@eecs.umich.edu 'sb' : ('signed int', 8), 1583101Sstever@eecs.umich.edu 'ub' : ('unsigned int', 8), 1593101Sstever@eecs.umich.edu 'sw' : ('signed int', 16), 1603101Sstever@eecs.umich.edu 'uw' : ('unsigned int', 16), 1613101Sstever@eecs.umich.edu 'sl' : ('signed int', 32), 1623101Sstever@eecs.umich.edu 'ul' : ('unsigned int', 32), 1633101Sstever@eecs.umich.edu 'sq' : ('signed int', 64), 1643101Sstever@eecs.umich.edu 'uq' : ('unsigned int', 64), 16513663Sandreas.sandberg@arm.com 'sf' : ('float', 32), 1663179Sstever@eecs.umich.edu 'df' : ('float', 64) 1673179Sstever@eecs.umich.edu}}; 1683179Sstever@eecs.umich.edu 1693179Sstever@eecs.umich.edudef operands {{ 1703179Sstever@eecs.umich.edu # Int regs default to unsigned, but code should not count on this. 1713179Sstever@eecs.umich.edu # For clarity, descriptions that depend on unsigned behavior should 1723101Sstever@eecs.umich.edu # explicitly specify '.uq'. 1733101Sstever@eecs.umich.edu 'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA', 1743101Sstever@eecs.umich.edu 'IsInteger', 1), 1753101Sstever@eecs.umich.edu 'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB', 17613663Sandreas.sandberg@arm.com 'IsInteger', 2), 1773179Sstever@eecs.umich.edu 'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC', 17813663Sandreas.sandberg@arm.com 'IsInteger', 3), 1793179Sstever@eecs.umich.edu 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), 1803179Sstever@eecs.umich.edu 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), 1813179Sstever@eecs.umich.edu 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 1823101Sstever@eecs.umich.edu 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 1833101Sstever@eecs.umich.edu 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), 1843101Sstever@eecs.umich.edu 'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1), 1853101Sstever@eecs.umich.edu 'FPCR': (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1), 18610195SGeoffrey.Blake@arm.com # The next two are hacks for non-full-system call-pal emulation 18710195SGeoffrey.Blake@arm.com 'R0': ('IntReg', 'uq', '0', None, 1), 18810195SGeoffrey.Blake@arm.com 'R16': ('IntReg', 'uq', '16', None, 1), 18910195SGeoffrey.Blake@arm.com 'R17': ('IntReg', 'uq', '17', None, 1), 19010195SGeoffrey.Blake@arm.com 'R18': ('IntReg', 'uq', '18', None, 1) 19110195SGeoffrey.Blake@arm.com}}; 19210195SGeoffrey.Blake@arm.com 19310195SGeoffrey.Blake@arm.com//////////////////////////////////////////////////////////////////// 19410195SGeoffrey.Blake@arm.com// 19510195SGeoffrey.Blake@arm.com// Basic instruction classes/templates/formats etc. 19610195SGeoffrey.Blake@arm.com// 1973101Sstever@eecs.umich.edu 1983101Sstever@eecs.umich.eduoutput header {{ 1993101Sstever@eecs.umich.edu// uncomment the following to get SimpleScalar-compatible disassembly 2003101Sstever@eecs.umich.edu// (useful for diffing output traces). 2013101Sstever@eecs.umich.edu// #define SS_COMPATIBLE_DISASSEMBLY 2023101Sstever@eecs.umich.edu 2033101Sstever@eecs.umich.edu /** 2043101Sstever@eecs.umich.edu * Base class for all Alpha static instructions. 2053101Sstever@eecs.umich.edu */ 2063101Sstever@eecs.umich.edu class AlphaStaticInst : public StaticInst 2073101Sstever@eecs.umich.edu { 2083101Sstever@eecs.umich.edu protected: 2093101Sstever@eecs.umich.edu 2103101Sstever@eecs.umich.edu /// Make AlphaISA register dependence tags directly visible in 2113101Sstever@eecs.umich.edu /// this class and derived classes. Maybe these should really 2123101Sstever@eecs.umich.edu /// live here and not in the AlphaISA namespace. 2133101Sstever@eecs.umich.edu enum DependenceTags { 2143101Sstever@eecs.umich.edu FP_Base_DepTag = AlphaISA::FP_Base_DepTag, 2153101Sstever@eecs.umich.edu Fpcr_DepTag = AlphaISA::Fpcr_DepTag, 2163101Sstever@eecs.umich.edu Uniq_DepTag = AlphaISA::Uniq_DepTag, 2173101Sstever@eecs.umich.edu Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag, 2183101Sstever@eecs.umich.edu Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag, 2193101Sstever@eecs.umich.edu IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag 2203101Sstever@eecs.umich.edu }; 2213101Sstever@eecs.umich.edu 2223101Sstever@eecs.umich.edu /// Constructor. 2233101Sstever@eecs.umich.edu AlphaStaticInst(const char *mnem, ExtMachInst _machInst, 2243101Sstever@eecs.umich.edu OpClass __opClass) 2253101Sstever@eecs.umich.edu : StaticInst(mnem, _machInst, __opClass) 2263101Sstever@eecs.umich.edu { 2273101Sstever@eecs.umich.edu } 2283101Sstever@eecs.umich.edu 2293101Sstever@eecs.umich.edu /// Print a register name for disassembly given the unique 2308927Sandreas.hansson@arm.com /// dependence tag number (FP or int). 2318927Sandreas.hansson@arm.com void printReg(std::ostream &os, int reg) const; 2328459SAli.Saidi@ARM.com 2338459SAli.Saidi@ARM.com std::string 2348459SAli.Saidi@ARM.com generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2358459SAli.Saidi@ARM.com }; 2368459SAli.Saidi@ARM.com}}; 2378459SAli.Saidi@ARM.com 2388459SAli.Saidi@ARM.comoutput decoder {{ 2393101Sstever@eecs.umich.edu void 24013716Sandreas.sandberg@arm.com AlphaStaticInst::printReg(std::ostream &os, int reg) const 2413101Sstever@eecs.umich.edu { 2423101Sstever@eecs.umich.edu if (reg < FP_Base_DepTag) { 2433101Sstever@eecs.umich.edu ccprintf(os, "r%d", reg); 2443101Sstever@eecs.umich.edu } 2453101Sstever@eecs.umich.edu else { 2463101Sstever@eecs.umich.edu ccprintf(os, "f%d", reg - FP_Base_DepTag); 2473101Sstever@eecs.umich.edu } 2483101Sstever@eecs.umich.edu } 2493101Sstever@eecs.umich.edu 2503101Sstever@eecs.umich.edu std::string 2513101Sstever@eecs.umich.edu AlphaStaticInst::generateDisassembly(Addr pc, 2523101Sstever@eecs.umich.edu const SymbolTable *symtab) const 2533101Sstever@eecs.umich.edu { 2543101Sstever@eecs.umich.edu std::stringstream ss; 2553101Sstever@eecs.umich.edu 2563101Sstever@eecs.umich.edu ccprintf(ss, "%-10s ", mnemonic); 2578459SAli.Saidi@ARM.com 2588459SAli.Saidi@ARM.com // just print the first two source regs... if there's 2598459SAli.Saidi@ARM.com // a third one, it's a read-modify-write dest (Rc), 2608459SAli.Saidi@ARM.com // e.g. for CMOVxx 2613101Sstever@eecs.umich.edu if (_numSrcRegs > 0) { 2623101Sstever@eecs.umich.edu printReg(ss, _srcRegIdx[0]); 2633101Sstever@eecs.umich.edu } 2643101Sstever@eecs.umich.edu if (_numSrcRegs > 1) { 2653101Sstever@eecs.umich.edu ss << ","; 2663101Sstever@eecs.umich.edu printReg(ss, _srcRegIdx[1]); 2673101Sstever@eecs.umich.edu } 2683101Sstever@eecs.umich.edu 2693101Sstever@eecs.umich.edu // just print the first dest... if there's a second one, 270 // it's generally implicit 271 if (_numDestRegs > 0) { 272 if (_numSrcRegs > 0) 273 ss << ","; 274 printReg(ss, _destRegIdx[0]); 275 } 276 277 return ss.str(); 278 } 279}}; 280 281// Declarations for execute() methods. 282def template BasicExecDeclare {{ 283 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; 284}}; 285 286// Basic instruction class declaration template. 287def template BasicDeclare {{ 288 /** 289 * Static instruction class for "%(mnemonic)s". 290 */ 291 class %(class_name)s : public %(base_class)s 292 { 293 public: 294 /// Constructor. 295 %(class_name)s(ExtMachInst machInst); 296 297 %(BasicExecDeclare)s 298 }; 299}}; 300 301// Basic instruction class constructor template. 302def template BasicConstructor {{ 303 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 304 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 305 { 306 %(constructor)s; 307 } 308}}; 309 310// Basic instruction class execute method template. 311def template BasicExecute {{ 312 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 313 Trace::InstRecord *traceData) const 314 { 315 Fault fault = NoFault; 316 317 %(fp_enable_check)s; 318 %(op_decl)s; 319 %(op_rd)s; 320 %(code)s; 321 322 if (fault == NoFault) { 323 %(op_wb)s; 324 } 325 326 return fault; 327 } 328}}; 329 330// Basic decode template. 331def template BasicDecode {{ 332 return new %(class_name)s(machInst); 333}}; 334 335// Basic decode template, passing mnemonic in as string arg to constructor. 336def template BasicDecodeWithMnemonic {{ 337 return new %(class_name)s("%(mnemonic)s", machInst); 338}}; 339 340// The most basic instruction format... used only for a few misc. insts 341def format BasicOperate(code, *flags) {{ 342 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags) 343 header_output = BasicDeclare.subst(iop) 344 decoder_output = BasicConstructor.subst(iop) 345 decode_block = BasicDecode.subst(iop) 346 exec_output = BasicExecute.subst(iop) 347}}; 348 349 350 351//////////////////////////////////////////////////////////////////// 352// 353// Nop 354// 355 356output header {{ 357 /** 358 * Static instruction class for no-ops. This is a leaf class. 359 */ 360 class Nop : public AlphaStaticInst 361 { 362 /// Disassembly of original instruction. 363 const std::string originalDisassembly; 364 365 public: 366 /// Constructor 367 Nop(const std::string _originalDisassembly, ExtMachInst _machInst) 368 : AlphaStaticInst("nop", _machInst, No_OpClass), 369 originalDisassembly(_originalDisassembly) 370 { 371 flags[IsNop] = true; 372 } 373 374 ~Nop() { } 375 376 std::string 377 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 378 379 %(BasicExecDeclare)s 380 }; 381 382 /// Helper function for decoding nops. Substitute Nop object 383 /// for original inst passed in as arg (and delete latter). 384 static inline 385 AlphaStaticInst * 386 makeNop(AlphaStaticInst *inst) 387 { 388 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst); 389 delete inst; 390 return nop; 391 } 392}}; 393 394output decoder {{ 395 std::string Nop::generateDisassembly(Addr pc, 396 const SymbolTable *symtab) const 397 { 398#ifdef SS_COMPATIBLE_DISASSEMBLY 399 return originalDisassembly; 400#else 401 return csprintf("%-10s (%s)", "nop", originalDisassembly); 402#endif 403 } 404}}; 405 406output exec {{ 407 Fault 408 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const 409 { 410 return NoFault; 411 } 412}}; 413 414// integer & FP operate instructions use Rc as dest, so check for 415// Rc == 31 to detect nops 416def template OperateNopCheckDecode {{ 417 { 418 AlphaStaticInst *i = new %(class_name)s(machInst); 419 if (RC == 31) { 420 i = makeNop(i); 421 } 422 return i; 423 } 424}}; 425 426// Like BasicOperate format, but generates NOP if RC/FC == 31 427def format BasicOperateWithNopCheck(code, *opt_args) {{ 428 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), 429 opt_args) 430 header_output = BasicDeclare.subst(iop) 431 decoder_output = BasicConstructor.subst(iop) 432 decode_block = OperateNopCheckDecode.subst(iop) 433 exec_output = BasicExecute.subst(iop) 434}}; 435 436// Integer instruction templates, formats, etc. 437##include "int.isa" 438 439// Floating-point instruction templates, formats, etc. 440##include "fp.isa" 441 442// Memory instruction templates, formats, etc. 443##include "mem.isa" 444 445// Branch/jump instruction templates, formats, etc. 446##include "branch.isa" 447 448// PAL instruction templates, formats, etc. 449##include "pal.isa" 450 451// Opcdec fault instruction templates, formats, etc. 452##include "opcdec.isa" 453 454// Unimplemented instruction templates, formats, etc. 455##include "unimp.isa" 456 457// Unknown instruction templates, formats, etc. 458##include "unknown.isa" 459 460// Execution utility functions 461##include "util.isa" 462 463// The actual decoder 464##include "decoder.isa" 465