main.isa revision 2649:2fb859a457a2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
29////////////////////////////////////////////////////////////////////
30//
31// Alpha ISA description file.
32//
33////////////////////////////////////////////////////////////////////
34
35
36////////////////////////////////////////////////////////////////////
37//
38// Output include file directives.
39//
40
41output header {{
42#include <sstream>
43#include <iostream>
44#include <iomanip>
45
46#include "config/ss_compatible_fp.hh"
47#include "cpu/static_inst.hh"
48#include "arch/alpha/faults.hh"
49#include "mem/request.hh"  // some constructors use MemReq flags
50}};
51
52output decoder {{
53#include "base/cprintf.hh"
54#include "base/fenv.hh"
55#include "base/loader/symtab.hh"
56#include "config/ss_compatible_fp.hh"
57#include "cpu/exec_context.hh"  // for Jump::branchTarget()
58
59#include <math.h>
60
61using namespace AlphaISA;
62}};
63
64output exec {{
65#include <math.h>
66
67#if FULL_SYSTEM
68#include "sim/pseudo_inst.hh"
69#endif
70#include "base/fenv.hh"
71#include "config/ss_compatible_fp.hh"
72#include "cpu/base.hh"
73#include "cpu/exetrace.hh"
74#include "sim/sim_exit.hh"
75#include "mem/packet_impl.hh"
76
77using namespace AlphaISA;
78}};
79
80////////////////////////////////////////////////////////////////////
81//
82// Namespace statement.  Everything below this line will be in the
83// AlphaISAInst namespace.
84//
85
86
87namespace AlphaISA;
88
89////////////////////////////////////////////////////////////////////
90//
91// Bitfield definitions.
92//
93
94// Universal (format-independent) fields
95def bitfield PALMODE    <32:32>;
96def bitfield OPCODE	<31:26>;
97def bitfield RA		<25:21>;
98def bitfield RB		<20:16>;
99
100// Memory format
101def signed bitfield MEMDISP <15: 0>; // displacement
102def        bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
103
104// Memory-format jumps
105def bitfield JMPFUNC	<15:14>; // function code (disp<15:14>)
106def bitfield JMPHINT	<13: 0>; // tgt Icache idx hint (disp<13:0>)
107
108// Branch format
109def signed bitfield BRDISP <20: 0>; // displacement
110
111// Integer operate format(s>;
112def bitfield INTIMM	<20:13>; // integer immediate (literal)
113def bitfield IMM	<12:12>; // immediate flag
114def bitfield INTFUNC	<11: 5>; // function code
115def bitfield RC		< 4: 0>; // dest reg
116
117// Floating-point operate format
118def bitfield FA		  <25:21>;
119def bitfield FB		  <20:16>;
120def bitfield FP_FULLFUNC  <15: 5>; // complete function code
121    def bitfield FP_TRAPMODE  <15:13>; // trapping mode
122    def bitfield FP_ROUNDMODE <12:11>; // rounding mode
123    def bitfield FP_TYPEFUNC  <10: 5>; // type+func: handiest for decoding
124        def bitfield FP_SRCTYPE   <10: 9>; // source reg type
125        def bitfield FP_SHORTFUNC < 8: 5>; // short function code
126        def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
127def bitfield FC		  < 4: 0>; // dest reg
128
129// PALcode format
130def bitfield PALFUNC	<25: 0>; // function code
131
132// EV5 PAL instructions:
133// HW_LD/HW_ST
134def bitfield HW_LDST_PHYS  <15>; // address is physical
135def bitfield HW_LDST_ALT   <14>; // use ALT_MODE IPR
136def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
137def bitfield HW_LDST_QUAD  <12>; // size: 0=32b, 1=64b
138def bitfield HW_LDST_VPTE  <11>; // HW_LD only: is PTE fetch
139def bitfield HW_LDST_LOCK  <10>; // HW_LD only: is load locked
140def bitfield HW_LDST_COND  <10>; // HW_ST only: is store conditional
141def signed bitfield HW_LDST_DISP  <9:0>; // signed displacement
142
143// HW_REI
144def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
145def bitfield HW_REI_MBZ <13: 0>; // must be zero
146
147// HW_MTPR/MW_MFPR
148def bitfield HW_IPR_IDX <15:0>;	 // IPR index
149
150// M5 instructions
151def bitfield M5FUNC <7:0>;
152
153def operand_types {{
154    'sb' : ('signed int', 8),
155    'ub' : ('unsigned int', 8),
156    'sw' : ('signed int', 16),
157    'uw' : ('unsigned int', 16),
158    'sl' : ('signed int', 32),
159    'ul' : ('unsigned int', 32),
160    'sq' : ('signed int', 64),
161    'uq' : ('unsigned int', 64),
162    'sf' : ('float', 32),
163    'df' : ('float', 64)
164}};
165
166def operands {{
167    # Int regs default to unsigned, but code should not count on this.
168    # For clarity, descriptions that depend on unsigned behavior should
169    # explicitly specify '.uq'.
170    'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA',
171           'IsInteger', 1),
172    'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB',
173           'IsInteger', 2),
174    'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC',
175           'IsInteger', 3),
176    'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
177    'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
178    'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
179    'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
180    'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
181    'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
182    'FPCR':  (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
183    # The next two are hacks for non-full-system call-pal emulation
184    'R0':  ('IntReg', 'uq', '0', None, 1),
185    'R16': ('IntReg', 'uq', '16', None, 1),
186    'R17': ('IntReg', 'uq', '17', None, 1),
187    'R18': ('IntReg', 'uq', '18', None, 1)
188}};
189
190////////////////////////////////////////////////////////////////////
191//
192// Basic instruction classes/templates/formats etc.
193//
194
195output header {{
196// uncomment the following to get SimpleScalar-compatible disassembly
197// (useful for diffing output traces).
198// #define SS_COMPATIBLE_DISASSEMBLY
199
200    /**
201     * Base class for all Alpha static instructions.
202     */
203    class AlphaStaticInst : public StaticInst
204    {
205      protected:
206
207        /// Make AlphaISA register dependence tags directly visible in
208        /// this class and derived classes.  Maybe these should really
209        /// live here and not in the AlphaISA namespace.
210        enum DependenceTags {
211            FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
212            Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
213            Uniq_DepTag = AlphaISA::Uniq_DepTag,
214            Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
215            Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
216            IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
217        };
218
219        /// Constructor.
220        AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
221                        OpClass __opClass)
222            : StaticInst(mnem, _machInst, __opClass)
223        {
224        }
225
226        /// Print a register name for disassembly given the unique
227        /// dependence tag number (FP or int).
228        void printReg(std::ostream &os, int reg) const;
229
230        std::string
231        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
232    };
233}};
234
235output decoder {{
236    void
237    AlphaStaticInst::printReg(std::ostream &os, int reg) const
238    {
239        if (reg < FP_Base_DepTag) {
240            ccprintf(os, "r%d", reg);
241        }
242        else {
243            ccprintf(os, "f%d", reg - FP_Base_DepTag);
244        }
245    }
246
247    std::string
248    AlphaStaticInst::generateDisassembly(Addr pc,
249                                         const SymbolTable *symtab) const
250    {
251        std::stringstream ss;
252
253        ccprintf(ss, "%-10s ", mnemonic);
254
255        // just print the first two source regs... if there's
256        // a third one, it's a read-modify-write dest (Rc),
257        // e.g. for CMOVxx
258        if (_numSrcRegs > 0) {
259            printReg(ss, _srcRegIdx[0]);
260        }
261        if (_numSrcRegs > 1) {
262            ss << ",";
263            printReg(ss, _srcRegIdx[1]);
264        }
265
266        // just print the first dest... if there's a second one,
267        // it's generally implicit
268        if (_numDestRegs > 0) {
269            if (_numSrcRegs > 0)
270                ss << ",";
271            printReg(ss, _destRegIdx[0]);
272        }
273
274        return ss.str();
275    }
276}};
277
278// Declarations for execute() methods.
279def template BasicExecDeclare {{
280    Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
281}};
282
283// Basic instruction class declaration template.
284def template BasicDeclare {{
285    /**
286     * Static instruction class for "%(mnemonic)s".
287     */
288    class %(class_name)s : public %(base_class)s
289    {
290      public:
291        /// Constructor.
292        %(class_name)s(ExtMachInst machInst);
293
294        %(BasicExecDeclare)s
295    };
296}};
297
298// Basic instruction class constructor template.
299def template BasicConstructor {{
300    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
301         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
302    {
303        %(constructor)s;
304    }
305}};
306
307// Basic instruction class execute method template.
308def template BasicExecute {{
309    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
310                                  Trace::InstRecord *traceData) const
311    {
312        Fault fault = NoFault;
313
314        %(fp_enable_check)s;
315        %(op_decl)s;
316        %(op_rd)s;
317        %(code)s;
318
319        if (fault == NoFault) {
320            %(op_wb)s;
321        }
322
323        return fault;
324    }
325}};
326
327// Basic decode template.
328def template BasicDecode {{
329    return new %(class_name)s(machInst);
330}};
331
332// Basic decode template, passing mnemonic in as string arg to constructor.
333def template BasicDecodeWithMnemonic {{
334    return new %(class_name)s("%(mnemonic)s", machInst);
335}};
336
337// The most basic instruction format... used only for a few misc. insts
338def format BasicOperate(code, *flags) {{
339    iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
340    header_output = BasicDeclare.subst(iop)
341    decoder_output = BasicConstructor.subst(iop)
342    decode_block = BasicDecode.subst(iop)
343    exec_output = BasicExecute.subst(iop)
344}};
345
346
347
348////////////////////////////////////////////////////////////////////
349//
350// Nop
351//
352
353output header {{
354    /**
355     * Static instruction class for no-ops.  This is a leaf class.
356     */
357    class Nop : public AlphaStaticInst
358    {
359        /// Disassembly of original instruction.
360        const std::string originalDisassembly;
361
362      public:
363        /// Constructor
364        Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
365            : AlphaStaticInst("nop", _machInst, No_OpClass),
366              originalDisassembly(_originalDisassembly)
367        {
368            flags[IsNop] = true;
369        }
370
371        ~Nop() { }
372
373        std::string
374        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
375
376        %(BasicExecDeclare)s
377    };
378
379    /// Helper function for decoding nops.  Substitute Nop object
380    /// for original inst passed in as arg (and delete latter).
381    static inline
382    AlphaStaticInst *
383    makeNop(AlphaStaticInst *inst)
384    {
385        AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
386        delete inst;
387        return nop;
388    }
389}};
390
391output decoder {{
392    std::string Nop::generateDisassembly(Addr pc,
393                                         const SymbolTable *symtab) const
394    {
395#ifdef SS_COMPATIBLE_DISASSEMBLY
396        return originalDisassembly;
397#else
398        return csprintf("%-10s (%s)", "nop", originalDisassembly);
399#endif
400    }
401}};
402
403output exec {{
404    Fault
405    Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
406    {
407        return NoFault;
408    }
409}};
410
411// integer & FP operate instructions use Rc as dest, so check for
412// Rc == 31 to detect nops
413def template OperateNopCheckDecode {{
414 {
415     AlphaStaticInst *i = new %(class_name)s(machInst);
416     if (RC == 31) {
417         i = makeNop(i);
418     }
419     return i;
420 }
421}};
422
423// Like BasicOperate format, but generates NOP if RC/FC == 31
424def format BasicOperateWithNopCheck(code, *opt_args) {{
425    iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
426                        opt_args)
427    header_output = BasicDeclare.subst(iop)
428    decoder_output = BasicConstructor.subst(iop)
429    decode_block = OperateNopCheckDecode.subst(iop)
430    exec_output = BasicExecute.subst(iop)
431}};
432
433// Integer instruction templates, formats, etc.
434##include "int.isa"
435
436// Floating-point instruction templates, formats, etc.
437##include "fp.isa"
438
439// Memory instruction templates, formats, etc.
440##include "mem.isa"
441
442// Branch/jump instruction templates, formats, etc.
443##include "branch.isa"
444
445// PAL instruction templates, formats, etc.
446##include "pal.isa"
447
448// Opcdec fault instruction templates, formats, etc.
449##include "opcdec.isa"
450
451// Unimplemented instruction templates, formats, etc.
452##include "unimp.isa"
453
454// Unknown instruction templates, formats, etc.
455##include "unknown.isa"
456
457// Execution utility functions
458##include "util.isa"
459
460// The actual decoder
461##include "decoder.isa"
462