int.isa revision 2649
110355SGeoffrey.Blake@arm.com// -*- mode:c++ -*- 28839Sandreas.hansson@arm.com 38839Sandreas.hansson@arm.com// Copyright (c) 2003-2005 The Regents of The University of Michigan 48839Sandreas.hansson@arm.com// All rights reserved. 58839Sandreas.hansson@arm.com// 68839Sandreas.hansson@arm.com// Redistribution and use in source and binary forms, with or without 78839Sandreas.hansson@arm.com// modification, are permitted provided that the following conditions are 88839Sandreas.hansson@arm.com// met: redistributions of source code must retain the above copyright 98839Sandreas.hansson@arm.com// notice, this list of conditions and the following disclaimer; 108839Sandreas.hansson@arm.com// redistributions in binary form must reproduce the above copyright 118839Sandreas.hansson@arm.com// notice, this list of conditions and the following disclaimer in the 128839Sandreas.hansson@arm.com// documentation and/or other materials provided with the distribution; 133101Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 148579Ssteve.reinhardt@amd.com// contributors may be used to endorse or promote products derived from 153101Sstever@eecs.umich.edu// this software without specific prior written permission. 163101Sstever@eecs.umich.edu// 173101Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 183101Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 193101Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 203101Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 213101Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 223101Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 233101Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 243101Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 253101Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 263101Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 273101Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 283101Sstever@eecs.umich.edu 293101Sstever@eecs.umich.edu//////////////////////////////////////////////////////////////////// 303101Sstever@eecs.umich.edu// 313101Sstever@eecs.umich.edu// Integer operate instructions 323101Sstever@eecs.umich.edu// 333101Sstever@eecs.umich.edu 343101Sstever@eecs.umich.eduoutput header {{ 353101Sstever@eecs.umich.edu /** 363101Sstever@eecs.umich.edu * Base class for integer immediate instructions. 373101Sstever@eecs.umich.edu */ 383101Sstever@eecs.umich.edu class IntegerImm : public AlphaStaticInst 393101Sstever@eecs.umich.edu { 403101Sstever@eecs.umich.edu protected: 413101Sstever@eecs.umich.edu /// Immediate operand value (unsigned 8-bit int). 427778Sgblack@eecs.umich.edu uint8_t imm; 438839Sandreas.hansson@arm.com 443101Sstever@eecs.umich.edu /// Constructor 453101Sstever@eecs.umich.edu IntegerImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 463101Sstever@eecs.umich.edu : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM) 473101Sstever@eecs.umich.edu { 483101Sstever@eecs.umich.edu } 493101Sstever@eecs.umich.edu 503101Sstever@eecs.umich.edu std::string 513101Sstever@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 523101Sstever@eecs.umich.edu }; 533101Sstever@eecs.umich.edu}}; 543101Sstever@eecs.umich.edu 553101Sstever@eecs.umich.eduoutput decoder {{ 563101Sstever@eecs.umich.edu std::string 573101Sstever@eecs.umich.edu IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const 583101Sstever@eecs.umich.edu { 593101Sstever@eecs.umich.edu std::stringstream ss; 603101Sstever@eecs.umich.edu 613101Sstever@eecs.umich.edu ccprintf(ss, "%-10s ", mnemonic); 623885Sbinkertn@umich.edu 633885Sbinkertn@umich.edu // just print the first source reg... if there's 644762Snate@binkert.org // a second one, it's a read-modify-write dest (Rc), 653885Sbinkertn@umich.edu // e.g. for CMOVxx 663885Sbinkertn@umich.edu if (_numSrcRegs > 0) { 677528Ssteve.reinhardt@amd.com printReg(ss, _srcRegIdx[0]); 683885Sbinkertn@umich.edu ss << ","; 694380Sbinkertn@umich.edu } 704167Sbinkertn@umich.edu 713102Sstever@eecs.umich.edu ss << (int)imm; 723101Sstever@eecs.umich.edu 734762Snate@binkert.org if (_numDestRegs > 0) { 744762Snate@binkert.org ss << ","; 754762Snate@binkert.org printReg(ss, _destRegIdx[0]); 764762Snate@binkert.org } 774762Snate@binkert.org 784762Snate@binkert.org return ss.str(); 794762Snate@binkert.org } 804762Snate@binkert.org}}; 814762Snate@binkert.org 825033Smilesck@eecs.umich.edu 835033Smilesck@eecs.umich.edudef template RegOrImmDecode {{ 845033Smilesck@eecs.umich.edu { 855033Smilesck@eecs.umich.edu AlphaStaticInst *i = 865033Smilesck@eecs.umich.edu (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst) 875033Smilesck@eecs.umich.edu : (AlphaStaticInst *)new %(class_name)s(machInst); 885033Smilesck@eecs.umich.edu if (RC == 31) { 895033Smilesck@eecs.umich.edu i = makeNop(i); 905033Smilesck@eecs.umich.edu } 915033Smilesck@eecs.umich.edu return i; 923101Sstever@eecs.umich.edu } 933101Sstever@eecs.umich.edu}}; 943101Sstever@eecs.umich.edu 955033Smilesck@eecs.umich.edu// Primary format for integer operate instructions: 9610267SGeoffrey.Blake@arm.com// - Generates both reg-reg and reg-imm versions if Rb_or_imm is used. 978596Ssteve.reinhardt@amd.com// - Generates NOP if RC == 31. 988596Ssteve.reinhardt@amd.comdef format IntegerOperate(code, *opt_flags) {{ 998596Ssteve.reinhardt@amd.com # If the code block contains 'Rb_or_imm', we define two instructions, 1008596Ssteve.reinhardt@amd.com # one using 'Rb' and one using 'imm', and have the decoder select 1017673Snate@binkert.org # the right one. 1027673Snate@binkert.org uses_imm = (code.find('Rb_or_imm') != -1) 1037673Snate@binkert.org if uses_imm: 1047673Snate@binkert.org orig_code = code 1058596Ssteve.reinhardt@amd.com # base code is reg version: 1068596Ssteve.reinhardt@amd.com # rewrite by substituting 'Rb' for 'Rb_or_imm' 1078596Ssteve.reinhardt@amd.com code = re.sub(r'Rb_or_imm', 'Rb', orig_code) 1087673Snate@binkert.org # generate immediate version by substituting 'imm' 1097673Snate@binkert.org # note that imm takes no extenstion, so we extend 1107673Snate@binkert.org # the regexp to replace any extension as well 1113101Sstever@eecs.umich.edu imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code) 1123101Sstever@eecs.umich.edu 1133101Sstever@eecs.umich.edu # generate declaration for register version 1143101Sstever@eecs.umich.edu cblk = CodeBlock(code) 1153101Sstever@eecs.umich.edu iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags) 1163101Sstever@eecs.umich.edu header_output = BasicDeclare.subst(iop) 11710380SAndrew.Bardsley@arm.com decoder_output = BasicConstructor.subst(iop) 11810380SAndrew.Bardsley@arm.com exec_output = BasicExecute.subst(iop) 11910380SAndrew.Bardsley@arm.com 12010380SAndrew.Bardsley@arm.com if uses_imm: 12110380SAndrew.Bardsley@arm.com # append declaration for imm version 12210380SAndrew.Bardsley@arm.com imm_cblk = CodeBlock(imm_code) 12310458Sandreas.hansson@arm.com imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk, 12410458Sandreas.hansson@arm.com opt_flags) 12510458Sandreas.hansson@arm.com header_output += BasicDeclare.subst(imm_iop) 12610458Sandreas.hansson@arm.com decoder_output += BasicConstructor.subst(imm_iop) 12710458Sandreas.hansson@arm.com exec_output += BasicExecute.subst(imm_iop) 12810458Sandreas.hansson@arm.com # decode checks IMM bit to pick correct version 12910458Sandreas.hansson@arm.com decode_block = RegOrImmDecode.subst(iop) 13010458Sandreas.hansson@arm.com else: 13110458Sandreas.hansson@arm.com # no imm version: just check for nop 13210458Sandreas.hansson@arm.com decode_block = OperateNopCheckDecode.subst(iop) 13310458Sandreas.hansson@arm.com}}; 13410458Sandreas.hansson@arm.com