decoder.isa revision 3467
12068SN/A// -*- mode:c++ -*-
22068SN/A
32188SN/A// Copyright (c) 2003-2006 The Regents of The University of Michigan
42068SN/A// All rights reserved.
52068SN/A//
62068SN/A// Redistribution and use in source and binary forms, with or without
72068SN/A// modification, are permitted provided that the following conditions are
82068SN/A// met: redistributions of source code must retain the above copyright
92068SN/A// notice, this list of conditions and the following disclaimer;
102068SN/A// redistributions in binary form must reproduce the above copyright
112068SN/A// notice, this list of conditions and the following disclaimer in the
122068SN/A// documentation and/or other materials provided with the distribution;
132068SN/A// neither the name of the copyright holders nor the names of its
142068SN/A// contributors may be used to endorse or promote products derived from
152068SN/A// this software without specific prior written permission.
162068SN/A//
172068SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182068SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192068SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202068SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212068SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222068SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232068SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242068SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252068SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262068SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272068SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282665Ssaidi@eecs.umich.edu//
292665Ssaidi@eecs.umich.edu// Authors: Steve Reinhardt
302068SN/A
312649Ssaidi@eecs.umich.edu////////////////////////////////////////////////////////////////////
322649Ssaidi@eecs.umich.edu//
332649Ssaidi@eecs.umich.edu// The actual decoder specification
342649Ssaidi@eecs.umich.edu//
352649Ssaidi@eecs.umich.edu
362068SN/Adecode OPCODE default Unknown::unknown() {
372068SN/A
382068SN/A    format LoadAddress {
392068SN/A        0x08: lda({{ Ra = Rb + disp; }});
402068SN/A        0x09: ldah({{ Ra = Rb + (disp << 16); }});
412068SN/A    }
422068SN/A
432068SN/A    format LoadOrNop {
442075SN/A        0x0a: ldbu({{ Ra.uq = Mem.ub; }});
452075SN/A        0x0c: ldwu({{ Ra.uq = Mem.uw; }});
462075SN/A        0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
472075SN/A        0x23: ldt({{ Fa = Mem.df; }});
482075SN/A        0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
492075SN/A        0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
502735Sktlim@umich.edu#ifdef USE_COPY
512069SN/A        0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
522069SN/A                                      {{ fault = xc->copySrcTranslate(EA); }},
532075SN/A                                      inst_flags = [IsMemRef, IsLoad, IsCopy]);
542735Sktlim@umich.edu#endif
552068SN/A    }
562068SN/A
572068SN/A    format LoadOrPrefetch {
582075SN/A        0x28: ldl({{ Ra.sl = Mem.sl; }});
592075SN/A        0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
602068SN/A        // IsFloating flag on lds gets the prefetch to disassemble
612068SN/A        // using f31 instead of r31... funcitonally it's unnecessary
622075SN/A        0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
632075SN/A                  pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
642068SN/A    }
652068SN/A
662068SN/A    format Store {
672075SN/A        0x0e: stb({{ Mem.ub = Ra<7:0>; }});
682075SN/A        0x0d: stw({{ Mem.uw = Ra<15:0>; }});
692075SN/A        0x2c: stl({{ Mem.ul = Ra<31:0>; }});
702075SN/A        0x2d: stq({{ Mem.uq = Ra.uq; }});
712075SN/A        0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
722075SN/A        0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
732075SN/A        0x27: stt({{ Mem.df = Fa; }});
742735Sktlim@umich.edu#ifdef USE_COPY
752069SN/A        0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
762069SN/A                                       {{ fault = xc->copy(EA); }},
772075SN/A                                       inst_flags = [IsMemRef, IsStore, IsCopy]);
782735Sktlim@umich.edu#endif
792068SN/A    }
802068SN/A
812068SN/A    format StoreCond {
822075SN/A        0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
832068SN/A                    {{
842069SN/A                        uint64_t tmp = write_result;
852068SN/A                        // see stq_c
862068SN/A                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
872336SN/A                    }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
882075SN/A        0x2f: stq_c({{ Mem.uq = Ra; }},
892068SN/A                    {{
902069SN/A                        uint64_t tmp = write_result;
912068SN/A                        // If the write operation returns 0 or 1, then
922068SN/A                        // this was a conventional store conditional,
932068SN/A                        // and the value indicates the success/failure
942068SN/A                        // of the operation.  If another value is
952068SN/A                        // returned, then this was a Turbolaser
962068SN/A                        // mailbox access, and we don't update the
972068SN/A                        // result register at all.
982068SN/A                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
992336SN/A                    }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
1002068SN/A    }
1012068SN/A
1022068SN/A    format IntegerOperate {
1032068SN/A
1042068SN/A        0x10: decode INTFUNC {	// integer arithmetic operations
1052068SN/A
1062068SN/A            0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1072068SN/A            0x40: addlv({{
1082068SN/A                uint32_t tmp  = Ra.sl + Rb_or_imm.sl;
1092068SN/A                // signed overflow occurs when operands have same sign
1102068SN/A                // and sign of result does not match.
1112068SN/A                if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1122147SN/A                    fault = new IntegerOverflowFault;
1132068SN/A                Rc.sl = tmp;
1142068SN/A            }});
1152068SN/A            0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1162068SN/A            0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1172068SN/A
1182068SN/A            0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1192068SN/A            0x60: addqv({{
1202068SN/A                uint64_t tmp = Ra + Rb_or_imm;
1212068SN/A                // signed overflow occurs when operands have same sign
1222068SN/A                // and sign of result does not match.
1232068SN/A                if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1242147SN/A                    fault = new IntegerOverflowFault;
1252068SN/A                Rc = tmp;
1262068SN/A            }});
1272068SN/A            0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
1282068SN/A            0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
1292068SN/A
1302068SN/A            0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
1312068SN/A            0x49: sublv({{
1322068SN/A                uint32_t tmp  = Ra.sl - Rb_or_imm.sl;
1332068SN/A                // signed overflow detection is same as for add,
1342068SN/A                // except we need to look at the *complemented*
1352068SN/A                // sign bit of the subtrahend (Rb), i.e., if the initial
1362068SN/A                // signs are the *same* then no overflow can occur
1372068SN/A                if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1382147SN/A                    fault = new IntegerOverflowFault;
1392068SN/A                Rc.sl = tmp;
1402068SN/A            }});
1412068SN/A            0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1422068SN/A            0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1432068SN/A
1442068SN/A            0x29: subq({{ Rc = Ra - Rb_or_imm; }});
1452068SN/A            0x69: subqv({{
1462068SN/A                uint64_t tmp  = Ra - Rb_or_imm;
1472068SN/A                // signed overflow detection is same as for add,
1482068SN/A                // except we need to look at the *complemented*
1492068SN/A                // sign bit of the subtrahend (Rb), i.e., if the initial
1502068SN/A                // signs are the *same* then no overflow can occur
1512068SN/A                if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1522147SN/A                    fault = new IntegerOverflowFault;
1532068SN/A                Rc = tmp;
1542068SN/A            }});
1552068SN/A            0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
1562068SN/A            0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
1572068SN/A
1582068SN/A            0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
1592068SN/A            0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
1602068SN/A            0x4d: cmplt({{ Rc = (Ra.sq <  Rb_or_imm.sq); }});
1612068SN/A            0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
1622068SN/A            0x1d: cmpult({{ Rc = (Ra.uq <  Rb_or_imm.uq); }});
1632068SN/A
1642068SN/A            0x0f: cmpbge({{
1652068SN/A                int hi = 7;
1662068SN/A                int lo = 0;
1672068SN/A                uint64_t tmp = 0;
1682068SN/A                for (int i = 0; i < 8; ++i) {
1692068SN/A                    tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
1702068SN/A                    hi += 8;
1712068SN/A                    lo += 8;
1722068SN/A                }
1732068SN/A                Rc = tmp;
1742068SN/A            }});
1752068SN/A        }
1762068SN/A
1772068SN/A        0x11: decode INTFUNC {	// integer logical operations
1782068SN/A
1792068SN/A            0x00: and({{ Rc = Ra & Rb_or_imm; }});
1802068SN/A            0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
1812068SN/A            0x20: bis({{ Rc = Ra | Rb_or_imm; }});
1822068SN/A            0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
1832068SN/A            0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
1842068SN/A            0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
1852068SN/A
1862068SN/A            // conditional moves
1872068SN/A            0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
1882068SN/A            0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
1892068SN/A            0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
1902068SN/A            0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
1912068SN/A            0x44: cmovlt({{ Rc = (Ra.sq <  0) ? Rb_or_imm : Rc; }});
1922068SN/A            0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
1932068SN/A            0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
1942068SN/A            0x66: cmovgt({{ Rc = (Ra.sq >  0) ? Rb_or_imm : Rc; }});
1952068SN/A
1962068SN/A            // For AMASK, RA must be R31.
1972068SN/A            0x61: decode RA {
1982068SN/A                31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
1992068SN/A            }
2002068SN/A
2012068SN/A            // For IMPLVER, RA must be R31 and the B operand
2022068SN/A            // must be the immediate value 1.
2032068SN/A            0x6c: decode RA {
2042068SN/A                31: decode IMM {
2052068SN/A                    1: decode INTIMM {
2062068SN/A                        // return EV5 for FULL_SYSTEM and EV6 otherwise
2072068SN/A                        1: implver({{
2082068SN/A#if FULL_SYSTEM
2092068SN/A                             Rc = 1;
2102068SN/A#else
2112068SN/A                             Rc = 2;
2122068SN/A#endif
2132068SN/A                        }});
2142068SN/A                    }
2152068SN/A                }
2162068SN/A            }
2172068SN/A
2182068SN/A#if FULL_SYSTEM
2192068SN/A            // The mysterious 11.25...
2202068SN/A            0x25: WarnUnimpl::eleven25();
2212068SN/A#endif
2222068SN/A        }
2232068SN/A
2242068SN/A        0x12: decode INTFUNC {
2252068SN/A            0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
2262068SN/A            0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
2272068SN/A            0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
2282068SN/A
2292068SN/A            0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
2302068SN/A            0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
2312068SN/A            0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
2322068SN/A            0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
2332068SN/A
2342068SN/A            0x52: mskwh({{
2352068SN/A                int bv = Rb_or_imm<2:0>;
2362068SN/A                Rc =  bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
2372068SN/A            }});
2382068SN/A            0x62: msklh({{
2392068SN/A                int bv = Rb_or_imm<2:0>;
2402068SN/A                Rc =  bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
2412068SN/A            }});
2422068SN/A            0x72: mskqh({{
2432068SN/A                int bv = Rb_or_imm<2:0>;
2442068SN/A                Rc =  bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
2452068SN/A            }});
2462068SN/A
2472068SN/A            0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
2482068SN/A            0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
2492068SN/A            0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
2502068SN/A            0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
2512068SN/A
2522068SN/A            0x5a: extwh({{
2532068SN/A                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
2542068SN/A            0x6a: extlh({{
2552068SN/A                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
2562068SN/A            0x7a: extqh({{
2572068SN/A                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
2582068SN/A
2592068SN/A            0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
2602068SN/A            0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
2612068SN/A            0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
2622068SN/A            0x3b: insql({{ Rc = Ra       << (Rb_or_imm<2:0> * 8); }});
2632068SN/A
2642068SN/A            0x57: inswh({{
2652068SN/A                int bv = Rb_or_imm<2:0>;
2662068SN/A                Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
2672068SN/A            }});
2682068SN/A            0x67: inslh({{
2692068SN/A                int bv = Rb_or_imm<2:0>;
2702068SN/A                Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
2712068SN/A            }});
2722068SN/A            0x77: insqh({{
2732068SN/A                int bv = Rb_or_imm<2:0>;
2742068SN/A                Rc = bv ? (Ra.uq       >> (64 - 8 * bv)) : 0;
2752068SN/A            }});
2762068SN/A
2772068SN/A            0x30: zap({{
2782068SN/A                uint64_t zapmask = 0;
2792068SN/A                for (int i = 0; i < 8; ++i) {
2802068SN/A                    if (Rb_or_imm<i:>)
2812068SN/A                        zapmask |= (mask(8) << (i * 8));
2822068SN/A                }
2832068SN/A                Rc = Ra & ~zapmask;
2842068SN/A            }});
2852068SN/A            0x31: zapnot({{
2862068SN/A                uint64_t zapmask = 0;
2872068SN/A                for (int i = 0; i < 8; ++i) {
2882068SN/A                    if (!Rb_or_imm<i:>)
2892068SN/A                        zapmask |= (mask(8) << (i * 8));
2902068SN/A                }
2912068SN/A                Rc = Ra & ~zapmask;
2922068SN/A            }});
2932068SN/A        }
2942068SN/A
2952068SN/A        0x13: decode INTFUNC {	// integer multiplies
2962068SN/A            0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
2972068SN/A            0x20: mulq({{ Rc    = Ra    * Rb_or_imm;    }}, IntMultOp);
2982068SN/A            0x30: umulh({{
2992068SN/A                uint64_t hi, lo;
3002068SN/A                mul128(Ra, Rb_or_imm, hi, lo);
3012068SN/A                Rc = hi;
3022068SN/A            }}, IntMultOp);
3032068SN/A            0x40: mullv({{
3042068SN/A                // 32-bit multiply with trap on overflow
3052068SN/A                int64_t Rax = Ra.sl;	// sign extended version of Ra.sl
3062068SN/A                int64_t Rbx = Rb_or_imm.sl;
3072068SN/A                int64_t tmp = Rax * Rbx;
3082068SN/A                // To avoid overflow, all the upper 32 bits must match
3092068SN/A                // the sign bit of the lower 32.  We code this as
3102068SN/A                // checking the upper 33 bits for all 0s or all 1s.
3112068SN/A                uint64_t sign_bits = tmp<63:31>;
3122068SN/A                if (sign_bits != 0 && sign_bits != mask(33))
3132147SN/A                    fault = new IntegerOverflowFault;
3142068SN/A                Rc.sl = tmp<31:0>;
3152068SN/A            }}, IntMultOp);
3162068SN/A            0x60: mulqv({{
3172068SN/A                // 64-bit multiply with trap on overflow
3182068SN/A                uint64_t hi, lo;
3192068SN/A                mul128(Ra, Rb_or_imm, hi, lo);
3202068SN/A                // all the upper 64 bits must match the sign bit of
3212068SN/A                // the lower 64
3222068SN/A                if (!((hi == 0 && lo<63:> == 0) ||
3232068SN/A                      (hi == mask(64) && lo<63:> == 1)))
3242147SN/A                    fault = new IntegerOverflowFault;
3252068SN/A                Rc = lo;
3262068SN/A            }}, IntMultOp);
3272068SN/A        }
3282068SN/A
3292068SN/A        0x1c: decode INTFUNC {
3302068SN/A            0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
3312068SN/A            0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
3322068SN/A            0x32: ctlz({{
3332068SN/A                             uint64_t count = 0;
3342068SN/A                             uint64_t temp = Rb;
3352068SN/A                             if (temp<63:32>) temp >>= 32; else count += 32;
3362068SN/A                             if (temp<31:16>) temp >>= 16; else count += 16;
3372068SN/A                             if (temp<15:8>) temp >>= 8; else count += 8;
3382068SN/A                             if (temp<7:4>) temp >>= 4; else count += 4;
3392068SN/A                             if (temp<3:2>) temp >>= 2; else count += 2;
3402068SN/A                             if (temp<1:1>) temp >>= 1; else count += 1;
3412068SN/A                             if ((temp<0:0>) != 0x1) count += 1;
3422068SN/A                             Rc = count;
3432068SN/A                           }}, IntAluOp);
3442068SN/A
3452068SN/A            0x33: cttz({{
3462068SN/A                             uint64_t count = 0;
3472068SN/A                             uint64_t temp = Rb;
3482068SN/A                             if (!(temp<31:0>)) { temp >>= 32; count += 32; }
3492068SN/A                             if (!(temp<15:0>)) { temp >>= 16; count += 16; }
3502068SN/A                             if (!(temp<7:0>)) { temp >>= 8; count += 8; }
3512068SN/A                             if (!(temp<3:0>)) { temp >>= 4; count += 4; }
3522068SN/A                             if (!(temp<1:0>)) { temp >>= 2; count += 2; }
3532068SN/A                             if (!(temp<0:0> & ULL(0x1))) count += 1;
3542068SN/A                             Rc = count;
3552068SN/A                           }}, IntAluOp);
3562068SN/A
3572068SN/A            format FailUnimpl {
3582068SN/A                0x30: ctpop();
3592068SN/A                0x31: perr();
3602068SN/A                0x34: unpkbw();
3612068SN/A                0x35: unpkbl();
3622068SN/A                0x36: pkwb();
3632068SN/A                0x37: pklb();
3642068SN/A                0x38: minsb8();
3652068SN/A                0x39: minsw4();
3662068SN/A                0x3a: minub8();
3672068SN/A                0x3b: minuw4();
3682068SN/A                0x3c: maxub8();
3692068SN/A                0x3d: maxuw4();
3702068SN/A                0x3e: maxsb8();
3712068SN/A                0x3f: maxsw4();
3722068SN/A            }
3732068SN/A
3742068SN/A            format BasicOperateWithNopCheck {
3752068SN/A                0x70: decode RB {
3762068SN/A                    31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
3772068SN/A                }
3782068SN/A                0x78: decode RB {
3792068SN/A                    31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
3802068SN/A                              FloatCvtOp);
3812068SN/A                }
3822068SN/A            }
3832068SN/A        }
3842068SN/A    }
3852068SN/A
3862068SN/A    // Conditional branches.
3872068SN/A    format CondBranch {
3882068SN/A        0x39: beq({{ cond = (Ra == 0); }});
3892068SN/A        0x3d: bne({{ cond = (Ra != 0); }});
3902068SN/A        0x3e: bge({{ cond = (Ra.sq >= 0); }});
3912068SN/A        0x3f: bgt({{ cond = (Ra.sq >  0); }});
3922068SN/A        0x3b: ble({{ cond = (Ra.sq <= 0); }});
3932068SN/A        0x3a: blt({{ cond = (Ra.sq < 0); }});
3942068SN/A        0x38: blbc({{ cond = ((Ra & 1) == 0); }});
3952068SN/A        0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
3962068SN/A
3972068SN/A        0x31: fbeq({{ cond = (Fa == 0); }});
3982068SN/A        0x35: fbne({{ cond = (Fa != 0); }});
3992068SN/A        0x36: fbge({{ cond = (Fa >= 0); }});
4002068SN/A        0x37: fbgt({{ cond = (Fa >  0); }});
4012068SN/A        0x33: fble({{ cond = (Fa <= 0); }});
4022068SN/A        0x32: fblt({{ cond = (Fa < 0); }});
4032068SN/A    }
4042068SN/A
4052068SN/A    // unconditional branches
4062068SN/A    format UncondBranch {
4072068SN/A        0x30: br();
4082068SN/A        0x34: bsr(IsCall);
4092068SN/A    }
4102068SN/A
4112068SN/A    // indirect branches
4122068SN/A    0x1a: decode JMPFUNC {
4132068SN/A        format Jump {
4142068SN/A            0: jmp();
4152068SN/A            1: jsr(IsCall);
4162068SN/A            2: ret(IsReturn);
4172068SN/A            3: jsr_coroutine(IsCall, IsReturn);
4182068SN/A        }
4192068SN/A    }
4202068SN/A
4212068SN/A    // Square root and integer-to-FP moves
4222068SN/A    0x14: decode FP_SHORTFUNC {
4232068SN/A        // Integer to FP register moves must have RB == 31
4242068SN/A        0x4: decode RB {
4252068SN/A            31: decode FP_FULLFUNC {
4262068SN/A                format BasicOperateWithNopCheck {
4272068SN/A                    0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
4282068SN/A                    0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
4292068SN/A                    0x014: FailUnimpl::itoff();	// VAX-format conversion
4302068SN/A                }
4312068SN/A            }
4322068SN/A        }
4332068SN/A
4342068SN/A        // Square root instructions must have FA == 31
4352068SN/A        0xb: decode FA {
4362068SN/A            31: decode FP_TYPEFUNC {
4372068SN/A                format FloatingPointOperate {
4382068SN/A#if SS_COMPATIBLE_FP
4392068SN/A                    0x0b: sqrts({{
4402068SN/A                        if (Fb < 0.0)
4412147SN/A                            fault = new ArithmeticFault;
4422068SN/A                        Fc = sqrt(Fb);
4432068SN/A                    }}, FloatSqrtOp);
4442068SN/A#else
4452068SN/A                    0x0b: sqrts({{
4462068SN/A                        if (Fb.sf < 0.0)
4472147SN/A                            fault = new ArithmeticFault;
4482068SN/A                        Fc.sf = sqrt(Fb.sf);
4492068SN/A                    }}, FloatSqrtOp);
4502068SN/A#endif
4512068SN/A                    0x2b: sqrtt({{
4522068SN/A                        if (Fb < 0.0)
4532147SN/A                            fault = new ArithmeticFault;
4542068SN/A                        Fc = sqrt(Fb);
4552068SN/A                    }}, FloatSqrtOp);
4562068SN/A                }
4572068SN/A            }
4582068SN/A        }
4592068SN/A
4602068SN/A        // VAX-format sqrtf and sqrtg are not implemented
4612068SN/A        0xa: FailUnimpl::sqrtfg();
4622068SN/A    }
4632068SN/A
4642068SN/A    // IEEE floating point
4652068SN/A    0x16: decode FP_SHORTFUNC_TOP2 {
4662068SN/A        // The top two bits of the short function code break this
4672068SN/A        // space into four groups: binary ops, compares, reserved, and
4682068SN/A        // conversions.  See Table 4-12 of AHB.  There are different
4692068SN/A        // special cases in these different groups, so we decode on
4702068SN/A        // these top two bits first just to select a decode strategy.
4712068SN/A        // Most of these instructions may have various trapping and
4722068SN/A        // rounding mode flags set; these are decoded in the
4732068SN/A        // FloatingPointDecode template used by the
4742068SN/A        // FloatingPointOperate format.
4752068SN/A
4762068SN/A        // add/sub/mul/div: just decode on the short function code
4772068SN/A        // and source type.  All valid trapping and rounding modes apply.
4782068SN/A        0: decode FP_TRAPMODE {
4792068SN/A            // check for valid trapping modes here
4802068SN/A            0,1,5,7: decode FP_TYPEFUNC {
4812068SN/A                   format FloatingPointOperate {
4822068SN/A#if SS_COMPATIBLE_FP
4832068SN/A                       0x00: adds({{ Fc = Fa + Fb; }});
4842068SN/A                       0x01: subs({{ Fc = Fa - Fb; }});
4852068SN/A                       0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
4862068SN/A                       0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
4872068SN/A#else
4882068SN/A                       0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
4892068SN/A                       0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
4902068SN/A                       0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
4912068SN/A                       0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
4922068SN/A#endif
4932068SN/A
4942068SN/A                       0x20: addt({{ Fc = Fa + Fb; }});
4952068SN/A                       0x21: subt({{ Fc = Fa - Fb; }});
4962068SN/A                       0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
4972068SN/A                       0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
4982068SN/A                   }
4992068SN/A             }
5002068SN/A        }
5012068SN/A
5022068SN/A        // Floating-point compare instructions must have the default
5032068SN/A        // rounding mode, and may use the default trapping mode or
5042068SN/A        // /SU.  Both trapping modes are treated the same by M5; the
5052068SN/A        // only difference on the real hardware (as far a I can tell)
5062068SN/A        // is that without /SU you'd get an imprecise trap if you
5072068SN/A        // tried to compare a NaN with something else (instead of an
5082068SN/A        // "unordered" result).
5092068SN/A        1: decode FP_FULLFUNC {
5102068SN/A            format BasicOperateWithNopCheck {
5112068SN/A                0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
5122068SN/A                                     FloatCmpOp);
5132068SN/A                0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
5142068SN/A                                     FloatCmpOp);
5152068SN/A                0x0a6, 0x5a6: cmptlt({{ Fc = (Fa <  Fb) ? 2.0 : 0.0; }},
5162068SN/A                                     FloatCmpOp);
5172068SN/A                0x0a4, 0x5a4: cmptun({{ // unordered
5182068SN/A                    Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
5192068SN/A                }}, FloatCmpOp);
5202068SN/A            }
5212068SN/A        }
5222068SN/A
5232068SN/A        // The FP-to-integer and integer-to-FP conversion insts
5242068SN/A        // require that FA be 31.
5252068SN/A        3: decode FA {
5262068SN/A            31: decode FP_TYPEFUNC {
5272068SN/A                format FloatingPointOperate {
5282068SN/A                    0x2f: decode FP_ROUNDMODE {
5292068SN/A                        format FPFixedRounding {
5302068SN/A                            // "chopped" i.e. round toward zero
5312068SN/A                            0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
5322068SN/A                                     Chopped);
5332068SN/A                            // round to minus infinity
5342068SN/A                            1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
5352068SN/A                                     MinusInfinity);
5362068SN/A                        }
5372068SN/A                      default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
5382068SN/A                    }
5392068SN/A
5402068SN/A                    // The cvtts opcode is overloaded to be cvtst if the trap
5412068SN/A                    // mode is 2 or 6 (which are not valid otherwise)
5422068SN/A                    0x2c: decode FP_FULLFUNC {
5432068SN/A                        format BasicOperateWithNopCheck {
5442068SN/A                            // trap on denorm version "cvtst/s" is
5452068SN/A                            // simulated same as cvtst
5462068SN/A                            0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
5472068SN/A                        }
5482068SN/A                      default: cvtts({{ Fc.sf = Fb; }});
5492068SN/A                    }
5502068SN/A
5512068SN/A                    // The trapping mode for integer-to-FP conversions
5522068SN/A                    // must be /SUI or nothing; /U and /SU are not
5532068SN/A                    // allowed.  The full set of rounding modes are
5542068SN/A                    // supported though.
5552068SN/A                    0x3c: decode FP_TRAPMODE {
5562068SN/A                        0,7: cvtqs({{ Fc.sf = Fb.sq; }});
5572068SN/A                    }
5582068SN/A                    0x3e: decode FP_TRAPMODE {
5592068SN/A                        0,7: cvtqt({{ Fc    = Fb.sq; }});
5602068SN/A                    }
5612068SN/A                }
5622068SN/A            }
5632068SN/A        }
5642068SN/A    }
5652068SN/A
5662068SN/A    // misc FP operate
5672068SN/A    0x17: decode FP_FULLFUNC {
5682068SN/A        format BasicOperateWithNopCheck {
5692068SN/A            0x010: cvtlq({{
5702068SN/A                Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
5712068SN/A            }});
5722068SN/A            0x030: cvtql({{
5732068SN/A                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
5742068SN/A            }});
5752068SN/A
5762068SN/A            // We treat the precise & imprecise trapping versions of
5772068SN/A            // cvtql identically.
5782068SN/A            0x130, 0x530: cvtqlv({{
5792068SN/A                // To avoid overflow, all the upper 32 bits must match
5802068SN/A                // the sign bit of the lower 32.  We code this as
5812068SN/A                // checking the upper 33 bits for all 0s or all 1s.
5822068SN/A                uint64_t sign_bits = Fb.uq<63:31>;
5832068SN/A                if (sign_bits != 0 && sign_bits != mask(33))
5842147SN/A                    fault = new IntegerOverflowFault;
5852068SN/A                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
5862068SN/A            }});
5872068SN/A
5882068SN/A            0x020: cpys({{  // copy sign
5892068SN/A                Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
5902068SN/A            }});
5912068SN/A            0x021: cpysn({{ // copy sign negated
5922068SN/A                Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
5932068SN/A            }});
5942068SN/A            0x022: cpyse({{ // copy sign and exponent
5952068SN/A                Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
5962068SN/A            }});
5972068SN/A
5982068SN/A            0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
5992068SN/A            0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
6002068SN/A            0x02c: fcmovlt({{ Fc = (Fa <  0) ? Fb : Fc; }});
6012068SN/A            0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
6022068SN/A            0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
6032068SN/A            0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
6042068SN/A
6052336SN/A            0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
6062336SN/A            0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
6072068SN/A        }
6082068SN/A    }
6092068SN/A
6102068SN/A    // miscellaneous mem-format ops
6112068SN/A    0x18: decode MEMFUNC {
6122068SN/A        format WarnUnimpl {
6132068SN/A            0x8000: fetch();
6142068SN/A            0xa000: fetch_m();
6152068SN/A            0xe800: ecb();
6162068SN/A        }
6172068SN/A
6182068SN/A        format MiscPrefetch {
6192068SN/A            0xf800: wh64({{ EA = Rb & ~ULL(63); }},
6202068SN/A                         {{ xc->writeHint(EA, 64, memAccessFlags); }},
6212075SN/A                         mem_flags = NO_FAULT,
6222075SN/A                         inst_flags = [IsMemRef, IsDataPrefetch,
6232075SN/A                                       IsStore, MemWriteOp]);
6242068SN/A        }
6252068SN/A
6262068SN/A        format BasicOperate {
6272068SN/A            0xc000: rpcc({{
6282068SN/A#if FULL_SYSTEM
6292068SN/A        /* Rb is a fake dependency so here is a fun way to get
6302068SN/A         * the parser to understand that.
6312068SN/A         */
6322159SN/A                Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
6332068SN/A
6342068SN/A#else
6352068SN/A                Ra = curTick;
6362068SN/A#endif
6372312SN/A            }}, IsUnverifiable);
6382068SN/A
6392068SN/A            // All of the barrier instructions below do nothing in
6402068SN/A            // their execute() methods (hence the empty code blocks).
6412068SN/A            // All of their functionality is hard-coded in the
6422068SN/A            // pipeline based on the flags IsSerializing,
6432068SN/A            // IsMemBarrier, and IsWriteBarrier.  In the current
6442068SN/A            // detailed CPU model, the execute() function only gets
6452068SN/A            // called at fetch, so there's no way to generate pipeline
6462068SN/A            // behavior at any other stage.  Once we go to an
6472068SN/A            // exec-in-exec CPU model we should be able to get rid of
6482068SN/A            // these flags and implement this behavior via the
6492068SN/A            // execute() methods.
6502068SN/A
6512068SN/A            // trapb is just a barrier on integer traps, where excb is
6522068SN/A            // a barrier on integer and FP traps.  "EXCB is thus a
6532068SN/A            // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
6542068SN/A            // them the same though.
6552292SN/A            0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
6562292SN/A            0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
6572068SN/A            0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
6582068SN/A            0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
6592068SN/A        }
6602068SN/A
6612068SN/A#if FULL_SYSTEM
6622068SN/A        format BasicOperate {
6632068SN/A            0xe000: rc({{
6643454Sgblack@eecs.umich.edu                Ra = IntrFlag;
6653454Sgblack@eecs.umich.edu                IntrFlag = 0;
6662704Sktlim@umich.edu            }}, IsNonSpeculative, IsUnverifiable);
6672068SN/A            0xf000: rs({{
6683454Sgblack@eecs.umich.edu                Ra = IntrFlag;
6693454Sgblack@eecs.umich.edu                IntrFlag = 1;
6702704Sktlim@umich.edu            }}, IsNonSpeculative, IsUnverifiable);
6712068SN/A        }
6722068SN/A#else
6732068SN/A        format FailUnimpl {
6742068SN/A            0xe000: rc();
6752068SN/A            0xf000: rs();
6762068SN/A        }
6772068SN/A#endif
6782068SN/A    }
6792068SN/A
6802068SN/A#if FULL_SYSTEM
6812068SN/A    0x00: CallPal::call_pal({{
6822068SN/A        if (!palValid ||
6832068SN/A            (palPriv
6842159SN/A             && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
6852068SN/A            // invalid pal function code, or attempt to do privileged
6862068SN/A            // PAL call in non-kernel mode
6872147SN/A            fault = new UnimplementedOpcodeFault;
6882068SN/A        }
6892068SN/A        else {
6902068SN/A            // check to see if simulator wants to do something special
6912068SN/A            // on this PAL call (including maybe suppress it)
6922068SN/A            bool dopal = xc->simPalCheck(palFunc);
6932068SN/A
6942068SN/A            if (dopal) {
6952159SN/A                xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
6962159SN/A                NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
6972068SN/A            }
6982068SN/A        }
6992068SN/A    }}, IsNonSpeculative);
7002068SN/A#else
7012068SN/A    0x00: decode PALFUNC {
7022068SN/A        format EmulatedCallPal {
7032068SN/A            0x00: halt ({{
7043144Shsul@eecs.umich.edu                exitSimLoop("halt instruction encountered");
7052068SN/A            }}, IsNonSpeculative);
7062068SN/A            0x83: callsys({{
7072562SN/A                xc->syscall(R0);
7082726Sktlim@umich.edu            }}, IsSerializeAfter, IsNonSpeculative);
7092068SN/A            // Read uniq reg into ABI return value register (r0)
7102336SN/A            0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
7112068SN/A            // Write uniq reg with value from ABI arg register (r16)
7122336SN/A            0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
7132068SN/A        }
7142068SN/A    }
7152068SN/A#endif
7162068SN/A
7172068SN/A#if FULL_SYSTEM
7182227SN/A    0x1b: decode PALMODE {
7192227SN/A        0: OpcdecFault::hw_st_quad();
7202227SN/A        1: decode HW_LDST_QUAD {
7212227SN/A            format HwLoad {
7222227SN/A                0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
7232227SN/A                1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
7242227SN/A            }
7252068SN/A        }
7262069SN/A    }
7272068SN/A
7282227SN/A    0x1f: decode PALMODE {
7292227SN/A        0: OpcdecFault::hw_st_cond();
7302227SN/A        format HwStore {
7312227SN/A            1: decode HW_LDST_COND {
7322227SN/A                0: decode HW_LDST_QUAD {
7332227SN/A                    0: hw_st({{ EA = (Rb + disp) & ~3; }},
7342227SN/A                {{ Mem.ul = Ra<31:0>; }}, L);
7352227SN/A                    1: hw_st({{ EA = (Rb + disp) & ~7; }},
7362227SN/A                {{ Mem.uq = Ra.uq; }}, Q);
7372227SN/A                }
7382227SN/A
7392227SN/A                1: FailUnimpl::hw_st_cond();
7402068SN/A            }
7412068SN/A        }
7422068SN/A    }
7432068SN/A
7442227SN/A    0x19: decode PALMODE {
7452227SN/A        0: OpcdecFault::hw_mfpr();
7462227SN/A        format HwMoveIPR {
7472227SN/A            1: hw_mfpr({{
7483464Sgblack@eecs.umich.edu                int miscRegIndex = (ipr_index < NumInternalProcRegs) ?
7493464Sgblack@eecs.umich.edu                        IprToMiscRegIndex[ipr_index] : -1;
7503464Sgblack@eecs.umich.edu                if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
7513466Sgblack@eecs.umich.edu                    miscRegIndex >= NumInternalProcRegs)
7523457Sgblack@eecs.umich.edu                        fault = new UnimplementedOpcodeFault;
7533457Sgblack@eecs.umich.edu                else
7543458Sgblack@eecs.umich.edu                    Ra = xc->readMiscRegWithEffect(miscRegIndex, fault);
7552336SN/A            }}, IsIprAccess);
7562227SN/A        }
7572227SN/A    }
7582227SN/A
7592227SN/A    0x1d: decode PALMODE {
7602227SN/A        0: OpcdecFault::hw_mtpr();
7612227SN/A        format HwMoveIPR {
7622227SN/A            1: hw_mtpr({{
7633464Sgblack@eecs.umich.edu                int miscRegIndex = (ipr_index < NumInternalProcRegs) ?
7643464Sgblack@eecs.umich.edu                        IprToMiscRegIndex[ipr_index] : -1;
7653467Sgblack@eecs.umich.edu                if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
7663466Sgblack@eecs.umich.edu                    miscRegIndex >= NumInternalProcRegs)
7673457Sgblack@eecs.umich.edu                        fault = new UnimplementedOpcodeFault;
7683457Sgblack@eecs.umich.edu                else
7693458Sgblack@eecs.umich.edu                    xc->setMiscRegWithEffect(miscRegIndex, Ra);
7702068SN/A                if (traceData) { traceData->setData(Ra); }
7712336SN/A            }}, IsIprAccess);
7722227SN/A        }
7732068SN/A    }
7742068SN/A
7752068SN/A    format BasicOperate {
7762227SN/A        0x1e: decode PALMODE {
7772227SN/A            0: OpcdecFault::hw_rei();
7782292SN/A            1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
7792227SN/A        }
7802068SN/A
7812068SN/A        // M5 special opcodes use the reserved 0x01 opcode space
7822068SN/A        0x01: decode M5FUNC {
7832068SN/A            0x00: arm({{
7842680Sktlim@umich.edu                AlphaPseudo::arm(xc->tcBase());
7852068SN/A            }}, IsNonSpeculative);
7862068SN/A            0x01: quiesce({{
7872680Sktlim@umich.edu                AlphaPseudo::quiesce(xc->tcBase());
7882292SN/A            }}, IsNonSpeculative, IsQuiesce);
7892188SN/A            0x02: quiesceNs({{
7902680Sktlim@umich.edu                AlphaPseudo::quiesceNs(xc->tcBase(), R16);
7912292SN/A            }}, IsNonSpeculative, IsQuiesce);
7922188SN/A            0x03: quiesceCycles({{
7932680Sktlim@umich.edu                AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
7942355SN/A            }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
7952188SN/A            0x04: quiesceTime({{
7962680Sktlim@umich.edu                R0 = AlphaPseudo::quiesceTime(xc->tcBase());
7972355SN/A            }}, IsNonSpeculative, IsUnverifiable);
7982068SN/A            0x10: ivlb({{
7992680Sktlim@umich.edu                AlphaPseudo::ivlb(xc->tcBase());
8002068SN/A            }}, No_OpClass, IsNonSpeculative);
8012068SN/A            0x11: ivle({{
8022680Sktlim@umich.edu                AlphaPseudo::ivle(xc->tcBase());
8032068SN/A            }}, No_OpClass, IsNonSpeculative);
8042068SN/A            0x20: m5exit_old({{
8052680Sktlim@umich.edu                AlphaPseudo::m5exit_old(xc->tcBase());
8062068SN/A            }}, No_OpClass, IsNonSpeculative);
8072068SN/A            0x21: m5exit({{
8082680Sktlim@umich.edu                AlphaPseudo::m5exit(xc->tcBase(), R16);
8092068SN/A            }}, No_OpClass, IsNonSpeculative);
8102358SN/A            0x31: loadsymbol({{
8113125Sktlim@umich.edu                AlphaPseudo::loadsymbol(xc->tcBase());
8122358SN/A            }}, No_OpClass, IsNonSpeculative);
8132680Sktlim@umich.edu            0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
8142068SN/A            0x40: resetstats({{
8152680Sktlim@umich.edu                AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
8162068SN/A            }}, IsNonSpeculative);
8172068SN/A            0x41: dumpstats({{
8182680Sktlim@umich.edu                AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
8192068SN/A            }}, IsNonSpeculative);
8202068SN/A            0x42: dumpresetstats({{
8212680Sktlim@umich.edu                AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17);
8222068SN/A            }}, IsNonSpeculative);
8232068SN/A            0x43: m5checkpoint({{
8242680Sktlim@umich.edu                AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17);
8252068SN/A            }}, IsNonSpeculative);
8262068SN/A            0x50: m5readfile({{
8272680Sktlim@umich.edu                R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18);
8282068SN/A            }}, IsNonSpeculative);
8292068SN/A            0x51: m5break({{
8302680Sktlim@umich.edu                AlphaPseudo::debugbreak(xc->tcBase());
8312068SN/A            }}, IsNonSpeculative);
8322068SN/A            0x52: m5switchcpu({{
8332680Sktlim@umich.edu                AlphaPseudo::switchcpu(xc->tcBase());
8342068SN/A            }}, IsNonSpeculative);
8352068SN/A            0x53: m5addsymbol({{
8362680Sktlim@umich.edu                AlphaPseudo::addsymbol(xc->tcBase(), R16, R17);
8372068SN/A            }}, IsNonSpeculative);
8382188SN/A            0x54: m5panic({{
8392284SN/A                panic("M5 panic instruction called at pc=%#x.", xc->readPC());
8402188SN/A            }}, IsNonSpeculative);
8413089Ssaidi@eecs.umich.edu            0x55: m5anBegin({{
8423089Ssaidi@eecs.umich.edu                AlphaPseudo::anBegin(xc->tcBase(), R16);
8433089Ssaidi@eecs.umich.edu            }}, IsNonSpeculative);
8443089Ssaidi@eecs.umich.edu            0x56: m5anWait({{
8453089Ssaidi@eecs.umich.edu                AlphaPseudo::anWait(xc->tcBase(), R16, R17);
8463089Ssaidi@eecs.umich.edu            }}, IsNonSpeculative);
8472068SN/A        }
8482068SN/A    }
8492068SN/A#endif
8502068SN/A}
851