branch.isa revision 2107
12068SN/A// -*- mode:c++ -*- 22068SN/A 32068SN/A// Copyright (c) 2003-2005 The Regents of The University of Michigan 42068SN/A// All rights reserved. 52068SN/A// 62068SN/A// Redistribution and use in source and binary forms, with or without 72068SN/A// modification, are permitted provided that the following conditions are 82068SN/A// met: redistributions of source code must retain the above copyright 92068SN/A// notice, this list of conditions and the following disclaimer; 102068SN/A// redistributions in binary form must reproduce the above copyright 112068SN/A// notice, this list of conditions and the following disclaimer in the 122068SN/A// documentation and/or other materials provided with the distribution; 132068SN/A// neither the name of the copyright holders nor the names of its 142068SN/A// contributors may be used to endorse or promote products derived from 152068SN/A// this software without specific prior written permission. 162068SN/A// 172068SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182068SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192068SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202068SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212068SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222068SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232068SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242068SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252068SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262068SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272068SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.eduoutput header {{ 302068SN/A 312649Ssaidi@eecs.umich.edu /** 322649Ssaidi@eecs.umich.edu * Base class for instructions whose disassembly is not purely a 332649Ssaidi@eecs.umich.edu * function of the machine instruction (i.e., it depends on the 342649Ssaidi@eecs.umich.edu * PC). This class overrides the disassemble() method to check 352649Ssaidi@eecs.umich.edu * the PC and symbol table values before re-using a cached 362068SN/A * disassembly string. This is necessary for branches and jumps, 372068SN/A * where the disassembly string includes the target address (which 382068SN/A * may depend on the PC and/or symbol table). 392068SN/A */ 402068SN/A class PCDependentDisassembly : public AlphaStaticInst 412068SN/A { 422068SN/A protected: 432068SN/A typedef TheISA::Addr Addr; 442068SN/A protected: 452068SN/A /// Cached program counter from last disassembly 462068SN/A mutable Addr cachedPC; 472068SN/A /// Cached symbol table pointer from last disassembly 482068SN/A mutable const SymbolTable *cachedSymtab; 492068SN/A 502068SN/A /// Constructor 512068SN/A PCDependentDisassembly(const char *mnem, MachInst _machInst, 522068SN/A OpClass __opClass) 532068SN/A : AlphaStaticInst(mnem, _machInst, __opClass), 542068SN/A cachedPC(0), cachedSymtab(0) 552068SN/A { 562227SN/A } 572068SN/A 582068SN/A const std::string & 592068SN/A disassemble(Addr pc, const SymbolTable *symtab) const; 602068SN/A }; 612068SN/A 622068SN/A /** 632068SN/A * Base class for branches (PC-relative control transfers), 642068SN/A * conditional or unconditional. 652068SN/A */ 662068SN/A class Branch : public PCDependentDisassembly 672068SN/A { 682068SN/A protected: 692068SN/A typedef TheISA::Addr Addr; 702068SN/A /// Displacement to target address (signed). 712068SN/A int32_t disp; 722068SN/A 732068SN/A /// Constructor. 742068SN/A Branch(const char *mnem, MachInst _machInst, OpClass __opClass) 752068SN/A : PCDependentDisassembly(mnem, _machInst, __opClass), 762068SN/A disp(BRDISP << 2) 772068SN/A { 782227SN/A } 792068SN/A 802068SN/A Addr branchTarget(Addr branchPC) const; 812068SN/A 822068SN/A std::string 832068SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 847720Sgblack@eecs.umich.edu }; 852068SN/A 862068SN/A /** 872068SN/A * Base class for jumps (register-indirect control transfers). In 882068SN/A * the Alpha ISA, these are always unconditional. 892068SN/A */ 902068SN/A class Jump : public PCDependentDisassembly 912068SN/A { 922068SN/A protected: 932068SN/A typedef TheISA::Addr Addr; 942068SN/A 952068SN/A /// Displacement to target address (signed). 962068SN/A int32_t disp; 972068SN/A 982068SN/A public: 992068SN/A /// Constructor 1002068SN/A Jump(const char *mnem, MachInst _machInst, OpClass __opClass) 1012068SN/A : PCDependentDisassembly(mnem, _machInst, __opClass), 1022068SN/A disp(BRDISP) 1032227SN/A { 1042068SN/A } 1052068SN/A 1062068SN/A Addr branchTarget(ExecContext *xc) const; 1072068SN/A 1082068SN/A std::string 1097720Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1102068SN/A }; 1112068SN/A}}; 1122068SN/A 1132068SN/Aoutput decoder {{ 1142068SN/A Addr 1152068SN/A Branch::branchTarget(Addr branchPC) const 1162068SN/A { 1177720Sgblack@eecs.umich.edu return branchPC + 4 + disp; 1187720Sgblack@eecs.umich.edu } 1192068SN/A 1207720Sgblack@eecs.umich.edu Addr 1212068SN/A Jump::branchTarget(ExecContext *xc) const 1222068SN/A { 1237720Sgblack@eecs.umich.edu Addr NPC = xc->readPC() + 4; 1242680Sktlim@umich.edu uint64_t Rb = xc->readIntReg(_srcRegIdx[0]); 1252068SN/A return (Rb & ~3) | (NPC & 1); 1267720Sgblack@eecs.umich.edu } 1272680Sktlim@umich.edu 1287720Sgblack@eecs.umich.edu const std::string & 1297720Sgblack@eecs.umich.edu PCDependentDisassembly::disassemble(Addr pc, 1302068SN/A const SymbolTable *symtab) const 1312068SN/A { 1322068SN/A if (!cachedDisassembly || 1332068SN/A pc != cachedPC || symtab != cachedSymtab) 1342068SN/A { 1352068SN/A if (cachedDisassembly) 1362068SN/A delete cachedDisassembly; 1372068SN/A 1382068SN/A cachedDisassembly = 1392068SN/A new std::string(generateDisassembly(pc, symtab)); 1402068SN/A cachedPC = pc; 1412068SN/A cachedSymtab = symtab; 1422068SN/A } 1432068SN/A 1442068SN/A return *cachedDisassembly; 1452068SN/A } 1462068SN/A 1472068SN/A std::string 1482068SN/A Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1492068SN/A { 1502068SN/A std::stringstream ss; 1512068SN/A 1522068SN/A ccprintf(ss, "%-10s ", mnemonic); 1532068SN/A 1542068SN/A // There's only one register arg (RA), but it could be 1552068SN/A // either a source (the condition for conditional 1562068SN/A // branches) or a destination (the link reg for 1572068SN/A // unconditional branches) 1582068SN/A if (_numSrcRegs > 0) { 1592068SN/A printReg(ss, _srcRegIdx[0]); 1602068SN/A ss << ","; 1612068SN/A } 1622068SN/A else if (_numDestRegs > 0) { 1632068SN/A printReg(ss, _destRegIdx[0]); 1642068SN/A ss << ","; 1652068SN/A } 1662068SN/A 1672068SN/A#ifdef SS_COMPATIBLE_DISASSEMBLY 1682068SN/A if (_numSrcRegs == 0 && _numDestRegs == 0) { 1692068SN/A printReg(ss, 31); 1702068SN/A ss << ","; 1712068SN/A } 1722068SN/A#endif 1732068SN/A 1742068SN/A Addr target = pc + 4 + disp; 1752068SN/A 1762068SN/A std::string str; 1772068SN/A if (symtab && symtab->findSymbol(target, str)) 1782068SN/A ss << str; 1792068SN/A else 1802068SN/A ccprintf(ss, "0x%x", target); 1812068SN/A 1822068SN/A return ss.str(); 1832068SN/A } 1842068SN/A 1852068SN/A std::string 1862068SN/A Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1872068SN/A { 1882068SN/A std::stringstream ss; 1892068SN/A 1902068SN/A ccprintf(ss, "%-10s ", mnemonic); 1912068SN/A 1922068SN/A#ifdef SS_COMPATIBLE_DISASSEMBLY 1932068SN/A if (_numDestRegs == 0) { 1942068SN/A printReg(ss, 31); 1952068SN/A ss << ","; 1962068SN/A } 1972068SN/A#endif 1982068SN/A 1992068SN/A if (_numDestRegs > 0) { 2002068SN/A printReg(ss, _destRegIdx[0]); 2012068SN/A ss << ","; 2022068SN/A } 2032068SN/A 2042068SN/A ccprintf(ss, "(r%d)", RB); 2052068SN/A 2062068SN/A return ss.str(); 2072068SN/A } 2082068SN/A}}; 2092068SN/A 2102068SN/Adef template JumpOrBranchDecode {{ 2112068SN/A return (RA == 31) 2122068SN/A ? (StaticInst *)new %(class_name)s(machInst) 2132068SN/A : (StaticInst *)new %(class_name)sAndLink(machInst); 2142068SN/A}}; 2152068SN/A 2162107SN/Adef format CondBranch(code) {{ 2172107SN/A code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n'; 2182068SN/A iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), 2192068SN/A ('IsDirectControl', 'IsCondControl')) 2202068SN/A header_output = BasicDeclare.subst(iop) 2217720Sgblack@eecs.umich.edu decoder_output = BasicConstructor.subst(iop) 2227720Sgblack@eecs.umich.edu decode_block = BasicDecode.subst(iop) 2237720Sgblack@eecs.umich.edu exec_output = BasicExecute.subst(iop) 2247720Sgblack@eecs.umich.edu}}; 2257794Sgblack@eecs.umich.edu 2267794Sgblack@eecs.umich.edulet {{ 2277794Sgblack@eecs.umich.edudef UncondCtrlBase(name, Name, base_class, npc_expr, flags): 2287720Sgblack@eecs.umich.edu # Declare basic control transfer w/o link (i.e. link reg is R31) 2293953Sstever@eecs.umich.edu nolink_code = 'NPC = %s;\n' % npc_expr 2302068SN/A nolink_iop = InstObjParams(name, Name, base_class, 2312068SN/A CodeBlock(nolink_code), flags) 2322068SN/A header_output = BasicDeclare.subst(nolink_iop) 2332068SN/A decoder_output = BasicConstructor.subst(nolink_iop) 2342068SN/A exec_output = BasicExecute.subst(nolink_iop) 2352068SN/A 2362068SN/A # Generate declaration of '*AndLink' version, append to decls 2372068SN/A link_code = 'Ra = NPC & ~3;\n' + nolink_code 2382068SN/A link_iop = InstObjParams(name, Name + 'AndLink', base_class, 2392068SN/A CodeBlock(link_code), flags) 2407794Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(link_iop) 2417720Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(link_iop) 2427794Sgblack@eecs.umich.edu exec_output += BasicExecute.subst(link_iop) 2432068SN/A 2442068SN/A # need to use link_iop for the decode template since it is expecting 2452068SN/A # the shorter version of class_name (w/o "AndLink") 2462068SN/A 2472068SN/A return (header_output, decoder_output, 2487794Sgblack@eecs.umich.edu JumpOrBranchDecode.subst(nolink_iop), exec_output) 2492068SN/A}}; 2507794Sgblack@eecs.umich.edu 2512068SN/Adef format UncondBranch(*flags) {{ 2522068SN/A flags += ('IsUncondControl', 'IsDirectControl') 2532068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 2542068SN/A UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags) 2552068SN/A}}; 2562068SN/A 2572068SN/Adef format Jump(*flags) {{ 2582068SN/A flags += ('IsUncondControl', 'IsIndirectControl') 2592068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 2602068SN/A UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags) 2612068SN/A}}; 2622068SN/A 2632068SN/A 2642068SN/A