isa.hh revision 7703:90299d921559 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ALPHA_ISA_HH__
32#define __ARCH_ALPHA_ISA_HH__
33
34#include <string.h>
35
36#include <string>
37#include <iostream>
38
39#include "arch/alpha/registers.hh"
40#include "arch/alpha/types.hh"
41#include "base/types.hh"
42
43class BaseCPU;
44class Checkpoint;
45class EventManager;
46class ThreadContext;
47
48namespace AlphaISA
49{
50    class ISA
51    {
52      public:
53        typedef uint64_t InternalProcReg;
54
55      protected:
56        uint64_t fpcr;       // floating point condition codes
57        uint64_t uniq;       // process-unique register
58        bool lock_flag;      // lock flag for LL/SC
59        Addr lock_addr;      // lock address for LL/SC
60        int intr_flag;
61
62        InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
63
64      protected:
65        InternalProcReg readIpr(int idx, ThreadContext *tc);
66        void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
67
68      public:
69
70        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
71        MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
72
73        void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
74                                ThreadID tid = 0);
75        void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
76                        ThreadID tid = 0);
77
78        void
79        clear()
80        {
81            fpcr = 0;
82            uniq = 0;
83            lock_flag = 0;
84            lock_addr = 0;
85            intr_flag = 0;
86            memset(ipr, 0, sizeof(ipr));
87        }
88
89        void serialize(EventManager *em, std::ostream &os);
90        void unserialize(EventManager *em, Checkpoint *cp,
91                const std::string &section);
92
93        void reset(std::string core_name, ThreadID num_threads,
94                   unsigned num_vpes, BaseCPU *_cpu)
95        { }
96
97
98        void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
99        { }
100
101        int
102        flattenIntIndex(int reg)
103        {
104            return reg;
105        }
106
107        int
108        flattenFloatIndex(int reg)
109        {
110            return reg;
111        }
112
113        ISA()
114        {
115            clear();
116            initializeIprTable();
117        }
118    };
119}
120
121#endif
122