isa.hh revision 6678:34191eea18c1 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ALPHA_ISA_HH__
32#define __ARCH_ALPHA_ISA_HH__
33
34#include <string>
35#include <iostream>
36
37#include "arch/alpha/registers.hh"
38#include "arch/alpha/types.hh"
39#include "base/types.hh"
40
41class BaseCPU;
42class Checkpoint;
43class EventManager;
44class ThreadContext;
45
46namespace AlphaISA
47{
48    class ISA
49    {
50      public:
51        typedef uint64_t InternalProcReg;
52
53      protected:
54        uint64_t fpcr;       // floating point condition codes
55        uint64_t uniq;       // process-unique register
56        bool lock_flag;      // lock flag for LL/SC
57        Addr lock_addr;      // lock address for LL/SC
58        int intr_flag;
59
60        InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
61
62      protected:
63        InternalProcReg readIpr(int idx, ThreadContext *tc);
64        void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
65
66      public:
67
68        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
69        MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
70
71        void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
72                                ThreadID tid = 0);
73        void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
74                        ThreadID tid = 0);
75
76        void
77        clear()
78        {
79            fpcr = 0;
80            uniq = 0;
81            lock_flag = 0;
82            lock_addr = 0;
83            intr_flag = 0;
84        }
85
86        void serialize(EventManager *em, std::ostream &os);
87        void unserialize(EventManager *em, Checkpoint *cp,
88                const std::string &section);
89
90        void reset(std::string core_name, ThreadID num_threads,
91                   unsigned num_vpes, BaseCPU *_cpu)
92        { }
93
94
95        void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
96        { }
97
98        int
99        flattenIntIndex(int reg)
100        {
101            return reg;
102        }
103
104        int
105        flattenFloatIndex(int reg)
106        {
107            return reg;
108        }
109
110        ISA()
111        {
112            clear();
113            initializeIprTable();
114        }
115    };
116}
117
118#endif
119