isa.hh revision 6330:786136379872 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ALPHA_ISA_HH__
32#define __ARCH_ALPHA_ISA_HH__
33
34#include <string>
35#include <iostream>
36
37#include "arch/alpha/registers.hh"
38#include "arch/alpha/types.hh"
39#include "base/types.hh"
40
41class BaseCPU;
42class Checkpoint;
43class EventManager;
44class ThreadContext;
45
46namespace AlphaISA
47{
48    class ISA
49    {
50      public:
51        typedef uint64_t InternalProcReg;
52
53      protected:
54        uint64_t fpcr;       // floating point condition codes
55        uint64_t uniq;       // process-unique register
56        bool lock_flag;      // lock flag for LL/SC
57        Addr lock_addr;      // lock address for LL/SC
58        int intr_flag;
59
60        InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
61
62      protected:
63        InternalProcReg readIpr(int idx, ThreadContext *tc);
64        void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
65
66      public:
67
68        // These functions should be removed once the simplescalar cpu
69        // model has been replaced.
70        int getInstAsid();
71        int getDataAsid();
72
73        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
74        MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
75
76        void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
77                                ThreadID tid = 0);
78        void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
79                        ThreadID tid = 0);
80
81        void
82        clear()
83        {
84            fpcr = 0;
85            uniq = 0;
86            lock_flag = 0;
87            lock_addr = 0;
88            intr_flag = 0;
89        }
90
91        void serialize(std::ostream &os);
92        void unserialize(Checkpoint *cp, const std::string &section);
93
94        void reset(std::string core_name, ThreadID num_threads,
95                   unsigned num_vpes, BaseCPU *_cpu)
96        { }
97
98
99        void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
100        { }
101
102        int
103        flattenIntIndex(int reg)
104        {
105            return reg;
106        }
107
108        int
109        flattenFloatIndex(int reg)
110        {
111            return reg;
112        }
113
114        ISA()
115        {
116            clear();
117            initializeIprTable();
118        }
119    };
120}
121
122#endif
123