isa.hh revision 10033:21c14a2b2117
19100SBrad.Beckmann@amd.com/* 29100SBrad.Beckmann@amd.com * Copyright (c) 2009 The Regents of The University of Michigan 39100SBrad.Beckmann@amd.com * All rights reserved. 49100SBrad.Beckmann@amd.com * 59100SBrad.Beckmann@amd.com * Redistribution and use in source and binary forms, with or without 69100SBrad.Beckmann@amd.com * modification, are permitted provided that the following conditions are 79100SBrad.Beckmann@amd.com * met: redistributions of source code must retain the above copyright 89100SBrad.Beckmann@amd.com * notice, this list of conditions and the following disclaimer; 99100SBrad.Beckmann@amd.com * redistributions in binary form must reproduce the above copyright 109100SBrad.Beckmann@amd.com * notice, this list of conditions and the following disclaimer in the 119100SBrad.Beckmann@amd.com * documentation and/or other materials provided with the distribution; 129100SBrad.Beckmann@amd.com * neither the name of the copyright holders nor the names of its 139100SBrad.Beckmann@amd.com * contributors may be used to endorse or promote products derived from 149100SBrad.Beckmann@amd.com * this software without specific prior written permission. 159100SBrad.Beckmann@amd.com * 169100SBrad.Beckmann@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179100SBrad.Beckmann@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189100SBrad.Beckmann@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199100SBrad.Beckmann@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209100SBrad.Beckmann@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219100SBrad.Beckmann@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229100SBrad.Beckmann@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239100SBrad.Beckmann@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249100SBrad.Beckmann@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259100SBrad.Beckmann@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269100SBrad.Beckmann@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279100SBrad.Beckmann@amd.com * 289100SBrad.Beckmann@amd.com * Authors: Gabe Black 299100SBrad.Beckmann@amd.com */ 309100SBrad.Beckmann@amd.com 319100SBrad.Beckmann@amd.com#ifndef __ARCH_ALPHA_ISA_HH__ 329100SBrad.Beckmann@amd.com#define __ARCH_ALPHA_ISA_HH__ 339100SBrad.Beckmann@amd.com 349100SBrad.Beckmann@amd.com#include <cstring> 359100SBrad.Beckmann@amd.com#include <iostream> 369100SBrad.Beckmann@amd.com#include <string> 379100SBrad.Beckmann@amd.com 389100SBrad.Beckmann@amd.com#include "arch/alpha/registers.hh" 399100SBrad.Beckmann@amd.com#include "arch/alpha/types.hh" 409100SBrad.Beckmann@amd.com#include "base/types.hh" 419100SBrad.Beckmann@amd.com#include "sim/sim_object.hh" 429100SBrad.Beckmann@amd.com#include "sim/system.hh" 439100SBrad.Beckmann@amd.com 449100SBrad.Beckmann@amd.comstruct AlphaISAParams; 459100SBrad.Beckmann@amd.comclass BaseCPU; 469100SBrad.Beckmann@amd.comclass Checkpoint; 479100SBrad.Beckmann@amd.comclass EventManager; 489100SBrad.Beckmann@amd.comclass ThreadContext; 499100SBrad.Beckmann@amd.com 509100SBrad.Beckmann@amd.comnamespace AlphaISA 519100SBrad.Beckmann@amd.com{ 529100SBrad.Beckmann@amd.com class ISA : public SimObject 539100SBrad.Beckmann@amd.com { 549100SBrad.Beckmann@amd.com public: 559100SBrad.Beckmann@amd.com typedef uint64_t InternalProcReg; 569100SBrad.Beckmann@amd.com typedef AlphaISAParams Params; 579100SBrad.Beckmann@amd.com 589100SBrad.Beckmann@amd.com protected: 599100SBrad.Beckmann@amd.com // Parent system 609100SBrad.Beckmann@amd.com System *system; 619100SBrad.Beckmann@amd.com 629100SBrad.Beckmann@amd.com uint64_t fpcr; // floating point condition codes 639100SBrad.Beckmann@amd.com uint64_t uniq; // process-unique register 649100SBrad.Beckmann@amd.com bool lock_flag; // lock flag for LL/SC 659100SBrad.Beckmann@amd.com Addr lock_addr; // lock address for LL/SC 669100SBrad.Beckmann@amd.com int intr_flag; 679100SBrad.Beckmann@amd.com 689100SBrad.Beckmann@amd.com InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs 699100SBrad.Beckmann@amd.com 709100SBrad.Beckmann@amd.com protected: 719100SBrad.Beckmann@amd.com InternalProcReg readIpr(int idx, ThreadContext *tc); 729100SBrad.Beckmann@amd.com void setIpr(int idx, InternalProcReg val, ThreadContext *tc); 739100SBrad.Beckmann@amd.com 749100SBrad.Beckmann@amd.com public: 759100SBrad.Beckmann@amd.com 769100SBrad.Beckmann@amd.com MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); 779100SBrad.Beckmann@amd.com MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); 789100SBrad.Beckmann@amd.com 799100SBrad.Beckmann@amd.com void setMiscRegNoEffect(int misc_reg, const MiscReg &val, 809100SBrad.Beckmann@amd.com ThreadID tid = 0); 819100SBrad.Beckmann@amd.com void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, 829100SBrad.Beckmann@amd.com ThreadID tid = 0); 839100SBrad.Beckmann@amd.com 849100SBrad.Beckmann@amd.com void 859100SBrad.Beckmann@amd.com clear() 869100SBrad.Beckmann@amd.com { 879100SBrad.Beckmann@amd.com fpcr = 0; 889100SBrad.Beckmann@amd.com uniq = 0; 899100SBrad.Beckmann@amd.com lock_flag = 0; 909100SBrad.Beckmann@amd.com lock_addr = 0; 919100SBrad.Beckmann@amd.com intr_flag = 0; 929100SBrad.Beckmann@amd.com memset(ipr, 0, sizeof(ipr)); 939100SBrad.Beckmann@amd.com } 949100SBrad.Beckmann@amd.com 959100SBrad.Beckmann@amd.com void serialize(std::ostream &os); 969100SBrad.Beckmann@amd.com void unserialize(Checkpoint *cp, const std::string §ion); 979100SBrad.Beckmann@amd.com 989100SBrad.Beckmann@amd.com int 999100SBrad.Beckmann@amd.com flattenIntIndex(int reg) 1009100SBrad.Beckmann@amd.com { 1019100SBrad.Beckmann@amd.com return reg; 1029100SBrad.Beckmann@amd.com } 1039100SBrad.Beckmann@amd.com 1049100SBrad.Beckmann@amd.com int 1059100SBrad.Beckmann@amd.com flattenFloatIndex(int reg) 1069100SBrad.Beckmann@amd.com { 1079100SBrad.Beckmann@amd.com return reg; 1089100SBrad.Beckmann@amd.com } 1099100SBrad.Beckmann@amd.com 1109100SBrad.Beckmann@amd.com // dummy 1119100SBrad.Beckmann@amd.com int 1129100SBrad.Beckmann@amd.com flattenCCIndex(int reg) 1139100SBrad.Beckmann@amd.com { 1149100SBrad.Beckmann@amd.com return reg; 1159100SBrad.Beckmann@amd.com } 1169100SBrad.Beckmann@amd.com 1179100SBrad.Beckmann@amd.com int 118 flattenMiscIndex(int reg) 119 { 120 return reg; 121 } 122 123 const Params *params() const; 124 125 ISA(Params *p); 126 127 void startup(ThreadContext *tc) {} 128 129 /// Explicitly import the otherwise hidden startup 130 using SimObject::startup; 131 }; 132} 133 134#endif 135