isa.hh revision 13582
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 36313Sgblack@eecs.umich.edu * All rights reserved. 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146313Sgblack@eecs.umich.edu * this software without specific prior written permission. 156313Sgblack@eecs.umich.edu * 166313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * Authors: Gabe Black 296313Sgblack@eecs.umich.edu */ 306313Sgblack@eecs.umich.edu 316313Sgblack@eecs.umich.edu#ifndef __ARCH_ALPHA_ISA_HH__ 326313Sgblack@eecs.umich.edu#define __ARCH_ALPHA_ISA_HH__ 336313Sgblack@eecs.umich.edu 348229Snate@binkert.org#include <cstring> 358229Snate@binkert.org#include <iostream> 366330Sgblack@eecs.umich.edu#include <string> 376330Sgblack@eecs.umich.edu 386330Sgblack@eecs.umich.edu#include "arch/alpha/registers.hh" 396313Sgblack@eecs.umich.edu#include "arch/alpha/types.hh" 406330Sgblack@eecs.umich.edu#include "base/types.hh" 4112106SRekai.GonzalezAlberquilla@arm.com#include "cpu/reg_class.hh" 429384SAndreas.Sandberg@arm.com#include "sim/sim_object.hh" 4310033SAli.Saidi@ARM.com#include "sim/system.hh" 446313Sgblack@eecs.umich.edu 459384SAndreas.Sandberg@arm.comstruct AlphaISAParams; 466330Sgblack@eecs.umich.educlass BaseCPU; 476313Sgblack@eecs.umich.educlass Checkpoint; 486313Sgblack@eecs.umich.educlass EventManager; 496330Sgblack@eecs.umich.educlass ThreadContext; 506313Sgblack@eecs.umich.edu 516313Sgblack@eecs.umich.edunamespace AlphaISA 526313Sgblack@eecs.umich.edu{ 539384SAndreas.Sandberg@arm.com class ISA : public SimObject 546313Sgblack@eecs.umich.edu { 556330Sgblack@eecs.umich.edu public: 566330Sgblack@eecs.umich.edu typedef uint64_t InternalProcReg; 579384SAndreas.Sandberg@arm.com typedef AlphaISAParams Params; 586330Sgblack@eecs.umich.edu 596313Sgblack@eecs.umich.edu protected: 6010033SAli.Saidi@ARM.com // Parent system 6110033SAli.Saidi@ARM.com System *system; 6210033SAli.Saidi@ARM.com 636330Sgblack@eecs.umich.edu uint64_t fpcr; // floating point condition codes 646330Sgblack@eecs.umich.edu uint64_t uniq; // process-unique register 656330Sgblack@eecs.umich.edu bool lock_flag; // lock flag for LL/SC 666330Sgblack@eecs.umich.edu Addr lock_addr; // lock address for LL/SC 676330Sgblack@eecs.umich.edu int intr_flag; 686330Sgblack@eecs.umich.edu 696330Sgblack@eecs.umich.edu InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs 706330Sgblack@eecs.umich.edu 716330Sgblack@eecs.umich.edu protected: 726330Sgblack@eecs.umich.edu InternalProcReg readIpr(int idx, ThreadContext *tc); 736330Sgblack@eecs.umich.edu void setIpr(int idx, InternalProcReg val, ThreadContext *tc); 746313Sgblack@eecs.umich.edu 756313Sgblack@eecs.umich.edu public: 766313Sgblack@eecs.umich.edu 7710698Sandreas.hansson@arm.com MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; 786330Sgblack@eecs.umich.edu MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); 796330Sgblack@eecs.umich.edu 8013582Sgabeblack@google.com void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0); 8113582Sgabeblack@google.com void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, 8213582Sgabeblack@google.com ThreadID tid=0); 836330Sgblack@eecs.umich.edu 846330Sgblack@eecs.umich.edu void 856330Sgblack@eecs.umich.edu clear() 866313Sgblack@eecs.umich.edu { 876330Sgblack@eecs.umich.edu fpcr = 0; 886330Sgblack@eecs.umich.edu uniq = 0; 896330Sgblack@eecs.umich.edu lock_flag = 0; 906330Sgblack@eecs.umich.edu lock_addr = 0; 916330Sgblack@eecs.umich.edu intr_flag = 0; 927702Sgblack@eecs.umich.edu memset(ipr, 0, sizeof(ipr)); 936313Sgblack@eecs.umich.edu } 946313Sgblack@eecs.umich.edu 9511168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 9611168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 976330Sgblack@eecs.umich.edu 9812106SRekai.GonzalezAlberquilla@arm.com RegId flattenRegId(const RegId& regId) const { return regId; } 9912106SRekai.GonzalezAlberquilla@arm.com 1006313Sgblack@eecs.umich.edu int 10110035Sandreas.hansson@arm.com flattenIntIndex(int reg) const 1026313Sgblack@eecs.umich.edu { 1036313Sgblack@eecs.umich.edu return reg; 1046313Sgblack@eecs.umich.edu } 1056313Sgblack@eecs.umich.edu 1066313Sgblack@eecs.umich.edu int 10710035Sandreas.hansson@arm.com flattenFloatIndex(int reg) const 1086313Sgblack@eecs.umich.edu { 1096313Sgblack@eecs.umich.edu return reg; 1106313Sgblack@eecs.umich.edu } 1116313Sgblack@eecs.umich.edu 11212109SRekai.GonzalezAlberquilla@arm.com int 11312109SRekai.GonzalezAlberquilla@arm.com flattenVecIndex(int reg) const 11412109SRekai.GonzalezAlberquilla@arm.com { 11512109SRekai.GonzalezAlberquilla@arm.com return reg; 11612109SRekai.GonzalezAlberquilla@arm.com } 11712109SRekai.GonzalezAlberquilla@arm.com 11812109SRekai.GonzalezAlberquilla@arm.com int 11912109SRekai.GonzalezAlberquilla@arm.com flattenVecElemIndex(int reg) const 12012109SRekai.GonzalezAlberquilla@arm.com { 12112109SRekai.GonzalezAlberquilla@arm.com return reg; 12212109SRekai.GonzalezAlberquilla@arm.com } 12312109SRekai.GonzalezAlberquilla@arm.com 1249920Syasuko.eckert@amd.com // dummy 1259920Syasuko.eckert@amd.com int 12610035Sandreas.hansson@arm.com flattenCCIndex(int reg) const 1279920Syasuko.eckert@amd.com { 1289920Syasuko.eckert@amd.com return reg; 1299920Syasuko.eckert@amd.com } 1309920Syasuko.eckert@amd.com 13110033SAli.Saidi@ARM.com int 13210035Sandreas.hansson@arm.com flattenMiscIndex(int reg) const 13310033SAli.Saidi@ARM.com { 13410033SAli.Saidi@ARM.com return reg; 13510033SAli.Saidi@ARM.com } 13610033SAli.Saidi@ARM.com 1379384SAndreas.Sandberg@arm.com const Params *params() const; 1389384SAndreas.Sandberg@arm.com 1399384SAndreas.Sandberg@arm.com ISA(Params *p); 1409461Snilay@cs.wisc.edu 1419461Snilay@cs.wisc.edu void startup(ThreadContext *tc) {} 1429553Sandreas.hansson@arm.com 1439553Sandreas.hansson@arm.com /// Explicitly import the otherwise hidden startup 1449553Sandreas.hansson@arm.com using SimObject::startup; 1456313Sgblack@eecs.umich.edu }; 1466313Sgblack@eecs.umich.edu} 1476313Sgblack@eecs.umich.edu 1486313Sgblack@eecs.umich.edu#endif 149