isa.hh revision 12106
16657Snate@binkert.org/* 26657Snate@binkert.org * Copyright (c) 2009 The Regents of The University of Michigan 36657Snate@binkert.org * All rights reserved. 46657Snate@binkert.org * 56657Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66657Snate@binkert.org * modification, are permitted provided that the following conditions are 76657Snate@binkert.org * met: redistributions of source code must retain the above copyright 86657Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96657Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106657Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116657Snate@binkert.org * documentation and/or other materials provided with the distribution; 126657Snate@binkert.org * neither the name of the copyright holders nor the names of its 136657Snate@binkert.org * contributors may be used to endorse or promote products derived from 146657Snate@binkert.org * this software without specific prior written permission. 156657Snate@binkert.org * 166657Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176657Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186657Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196657Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206657Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216657Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226657Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236657Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246657Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256657Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266657Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276657Snate@binkert.org * 286657Snate@binkert.org * Authors: Gabe Black 296657Snate@binkert.org */ 306657Snate@binkert.org 316657Snate@binkert.org#ifndef __ARCH_ALPHA_ISA_HH__ 326657Snate@binkert.org#define __ARCH_ALPHA_ISA_HH__ 336999Snate@binkert.org 348452Snate@binkert.org#include <cstring> 356657Snate@binkert.org#include <iostream> 366657Snate@binkert.org#include <string> 376657Snate@binkert.org 386657Snate@binkert.org#include "arch/alpha/registers.hh" 396657Snate@binkert.org#include "arch/alpha/types.hh" 406657Snate@binkert.org#include "base/types.hh" 419219Spower.jg@gmail.com#include "cpu/reg_class.hh" 428454Snate@binkert.org#include "sim/sim_object.hh" 438454Snate@binkert.org#include "sim/system.hh" 448453Snate@binkert.org 456999Snate@binkert.orgstruct AlphaISAParams; 469219Spower.jg@gmail.comclass BaseCPU; 476999Snate@binkert.orgclass Checkpoint; 488454Snate@binkert.orgclass EventManager; 498454Snate@binkert.orgclass ThreadContext; 508454Snate@binkert.org 518454Snate@binkert.orgnamespace AlphaISA 528454Snate@binkert.org{ 538454Snate@binkert.org class ISA : public SimObject 548454Snate@binkert.org { 558453Snate@binkert.org public: 568453Snate@binkert.org typedef uint64_t InternalProcReg; 578453Snate@binkert.org typedef AlphaISAParams Params; 588453Snate@binkert.org 596999Snate@binkert.org protected: 606999Snate@binkert.org // Parent system 616999Snate@binkert.org System *system; 626999Snate@binkert.org 636657Snate@binkert.org uint64_t fpcr; // floating point condition codes 648453Snate@binkert.org uint64_t uniq; // process-unique register 658454Snate@binkert.org bool lock_flag; // lock flag for LL/SC 668454Snate@binkert.org Addr lock_addr; // lock address for LL/SC 676657Snate@binkert.org int intr_flag; 689219Spower.jg@gmail.com 699219Spower.jg@gmail.com InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs 706657Snate@binkert.org 718453Snate@binkert.org protected: 728453Snate@binkert.org InternalProcReg readIpr(int idx, ThreadContext *tc); 736657Snate@binkert.org void setIpr(int idx, InternalProcReg val, ThreadContext *tc); 746657Snate@binkert.org 756714Ssteve.reinhardt@amd.com public: 766714Ssteve.reinhardt@amd.com 776657Snate@binkert.org MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; 786657Snate@binkert.org MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); 796657Snate@binkert.org 808454Snate@binkert.org void setMiscRegNoEffect(int misc_reg, const MiscReg &val, 816657Snate@binkert.org ThreadID tid = 0); 826714Ssteve.reinhardt@amd.com void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, 836657Snate@binkert.org ThreadID tid = 0); 846657Snate@binkert.org 856657Snate@binkert.org void 866657Snate@binkert.org clear() 876657Snate@binkert.org { 886657Snate@binkert.org fpcr = 0; 896657Snate@binkert.org uniq = 0; 906657Snate@binkert.org lock_flag = 0; 916657Snate@binkert.org lock_addr = 0; 926657Snate@binkert.org intr_flag = 0; 936657Snate@binkert.org memset(ipr, 0, sizeof(ipr)); 946657Snate@binkert.org } 956657Snate@binkert.org 966657Snate@binkert.org void serialize(CheckpointOut &cp) const override; 976657Snate@binkert.org void unserialize(CheckpointIn &cp) override; 986657Snate@binkert.org 996657Snate@binkert.org RegId flattenRegId(const RegId& regId) const { return regId; } 1008454Snate@binkert.org 1018454Snate@binkert.org int 1026657Snate@binkert.org flattenIntIndex(int reg) const 1036657Snate@binkert.org { 1046657Snate@binkert.org return reg; 1056657Snate@binkert.org } 1066657Snate@binkert.org 1076657Snate@binkert.org int 1086657Snate@binkert.org flattenFloatIndex(int reg) const 1096657Snate@binkert.org { 1106657Snate@binkert.org return reg; 1118086SBrad.Beckmann@amd.com } 1126657Snate@binkert.org 1137567SBrad.Beckmann@amd.com // dummy 1146657Snate@binkert.org int 1156657Snate@binkert.org flattenCCIndex(int reg) const 1166657Snate@binkert.org { 1176657Snate@binkert.org return reg; 1186882SBrad.Beckmann@amd.com } 1196657Snate@binkert.org 1207839Snilay@cs.wisc.edu int 1217839Snilay@cs.wisc.edu flattenMiscIndex(int reg) const 1226657Snate@binkert.org { 1236657Snate@binkert.org return reg; 1246657Snate@binkert.org } 1256657Snate@binkert.org 1266657Snate@binkert.org const Params *params() const; 1276657Snate@binkert.org 1287839Snilay@cs.wisc.edu ISA(Params *p); 1296657Snate@binkert.org 1306657Snate@binkert.org void startup(ThreadContext *tc) {} 1316657Snate@binkert.org 1326657Snate@binkert.org /// Explicitly import the otherwise hidden startup 1336657Snate@binkert.org using SimObject::startup; 1346657Snate@binkert.org }; 1356657Snate@binkert.org} 1366657Snate@binkert.org 1376657Snate@binkert.org#endif 1386657Snate@binkert.org