isa.cc revision 12334:e0ab29a34764 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/alpha/isa.hh"
32
33#include <cassert>
34
35#include "base/logging.hh"
36#include "cpu/thread_context.hh"
37#include "params/AlphaISA.hh"
38#include "sim/serialize.hh"
39
40namespace AlphaISA
41{
42
43ISA::ISA(Params *p)
44    : SimObject(p), system(p->system)
45{
46    clear();
47    initializeIprTable();
48}
49
50const AlphaISAParams *
51ISA::params() const
52{
53    return dynamic_cast<const Params *>(_params);
54}
55
56void
57ISA::serialize(CheckpointOut &cp) const
58{
59    SERIALIZE_SCALAR(fpcr);
60    SERIALIZE_SCALAR(uniq);
61    SERIALIZE_SCALAR(lock_flag);
62    SERIALIZE_SCALAR(lock_addr);
63    SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
64}
65
66void
67ISA::unserialize(CheckpointIn &cp)
68{
69    UNSERIALIZE_SCALAR(fpcr);
70    UNSERIALIZE_SCALAR(uniq);
71    UNSERIALIZE_SCALAR(lock_flag);
72    UNSERIALIZE_SCALAR(lock_addr);
73    UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
74}
75
76
77MiscReg
78ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
79{
80    switch (misc_reg) {
81      case MISCREG_FPCR:
82        return fpcr;
83      case MISCREG_UNIQ:
84        return uniq;
85      case MISCREG_LOCKFLAG:
86        return lock_flag;
87      case MISCREG_LOCKADDR:
88        return lock_addr;
89      case MISCREG_INTR:
90        return intr_flag;
91      default:
92        assert(misc_reg < NumInternalProcRegs);
93        return ipr[misc_reg];
94    }
95}
96
97MiscReg
98ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
99{
100    switch (misc_reg) {
101      case MISCREG_FPCR:
102        return fpcr;
103      case MISCREG_UNIQ:
104        return uniq;
105      case MISCREG_LOCKFLAG:
106        return lock_flag;
107      case MISCREG_LOCKADDR:
108        return lock_addr;
109      case MISCREG_INTR:
110        return intr_flag;
111      default:
112        return readIpr(misc_reg, tc);
113    }
114}
115
116void
117ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
118{
119    switch (misc_reg) {
120      case MISCREG_FPCR:
121        fpcr = val;
122        return;
123      case MISCREG_UNIQ:
124        uniq = val;
125        return;
126      case MISCREG_LOCKFLAG:
127        lock_flag = val;
128        return;
129      case MISCREG_LOCKADDR:
130        lock_addr = val;
131        return;
132      case MISCREG_INTR:
133        intr_flag = val;
134        return;
135      default:
136        assert(misc_reg < NumInternalProcRegs);
137        ipr[misc_reg] = val;
138        return;
139    }
140}
141
142void
143ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
144                ThreadID tid)
145{
146    switch (misc_reg) {
147      case MISCREG_FPCR:
148        fpcr = val;
149        return;
150      case MISCREG_UNIQ:
151        uniq = val;
152        return;
153      case MISCREG_LOCKFLAG:
154        lock_flag = val;
155        return;
156      case MISCREG_LOCKADDR:
157        lock_addr = val;
158        return;
159      case MISCREG_INTR:
160        intr_flag = val;
161        return;
162      default:
163        setIpr(misc_reg, val, tc);
164        return;
165    }
166}
167
168}
169
170AlphaISA::ISA *
171AlphaISAParams::create()
172{
173    return new AlphaISA::ISA(this);
174}
175