isa.cc revision 7678
12SN/A/* 22188SN/A * Copyright (c) 2009 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Gabe Black 292665SN/A */ 302665SN/A 312665SN/A#include <cassert> 322SN/A 332SN/A#include "arch/alpha/isa.hh" 342SN/A#include "base/misc.hh" 352SN/A#include "cpu/thread_context.hh" 362465SN/A 371717SN/Anamespace AlphaISA 382683Sktlim@umich.edu{ 392680SN/A 405529Snate@binkert.orgvoid 412SN/AISA::serialize(EventManager *em, std::ostream &os) 421858SN/A{ 433565Sgblack@eecs.umich.edu SERIALIZE_SCALAR(fpcr); 445529Snate@binkert.org SERIALIZE_SCALAR(uniq); 451917SN/A SERIALIZE_SCALAR(lock_flag); 461070SN/A SERIALIZE_SCALAR(lock_addr); 471917SN/A SERIALIZE_ARRAY(ipr, NumInternalProcRegs); 482188SN/A} 491917SN/A 502290SN/Avoid 511070SN/AISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion) 521917SN/A{ 532SN/A UNSERIALIZE_SCALAR(fpcr); 545529Snate@binkert.org UNSERIALIZE_SCALAR(uniq); 55360SN/A UNSERIALIZE_SCALAR(lock_flag); 562519SN/A UNSERIALIZE_SCALAR(lock_addr); 572SN/A UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs); 582SN/A} 592SN/A 602SN/A 612SN/AMiscReg 621858SN/AISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) 632683Sktlim@umich.edu{ 643453Sgblack@eecs.umich.edu switch (misc_reg) { 652683Sktlim@umich.edu case MISCREG_FPCR: 665712Shsul@eecs.umich.edu return fpcr; 672683Sktlim@umich.edu case MISCREG_UNIQ: 682521SN/A return uniq; 692SN/A case MISCREG_LOCKFLAG: 702683Sktlim@umich.edu return lock_flag; 712190SN/A case MISCREG_LOCKADDR: 722680SN/A return lock_addr; 732290SN/A case MISCREG_INTR: 742526SN/A return intr_flag; 751917SN/A default: 765529Snate@binkert.org assert(misc_reg < NumInternalProcRegs); 771982SN/A return ipr[misc_reg]; 781917SN/A } 792683Sktlim@umich.edu} 802683Sktlim@umich.edu 811917SN/AMiscReg 821917SN/AISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) 831917SN/A{ 841917SN/A switch (misc_reg) { 851917SN/A case MISCREG_FPCR: 861917SN/A return fpcr; 871917SN/A case MISCREG_UNIQ: 881917SN/A return uniq; 892521SN/A case MISCREG_LOCKFLAG: 905482Snate@binkert.org return lock_flag; 913548Sgblack@eecs.umich.edu case MISCREG_LOCKADDR: 922SN/A return lock_addr; 932SN/A case MISCREG_INTR: 944997Sgblack@eecs.umich.edu return intr_flag; 954997Sgblack@eecs.umich.edu default: 965712Shsul@eecs.umich.edu return readIpr(misc_reg, tc); 974997Sgblack@eecs.umich.edu } 982SN/A} 992526SN/A 1002683Sktlim@umich.eduvoid 1012SN/AISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) 1022190SN/A{ 1032862Sktlim@umich.edu switch (misc_reg) { 1042862Sktlim@umich.edu case MISCREG_FPCR: 1052864Sktlim@umich.edu fpcr = val; 1062862Sktlim@umich.edu return; 1075712Shsul@eecs.umich.edu case MISCREG_UNIQ: 1082862Sktlim@umich.edu uniq = val; 1095712Shsul@eecs.umich.edu return; 1102862Sktlim@umich.edu case MISCREG_LOCKFLAG: 1112190SN/A lock_flag = val; 1122683Sktlim@umich.edu return; 1132862Sktlim@umich.edu case MISCREG_LOCKADDR: 1142190SN/A lock_addr = val; 1152190SN/A return; 1162683Sktlim@umich.edu case MISCREG_INTR: 1171070SN/A intr_flag = val; 1183486Sktlim@umich.edu return; 1193486Sktlim@umich.edu default: 1203486Sktlim@umich.edu assert(misc_reg < NumInternalProcRegs); 1213486Sktlim@umich.edu ipr[misc_reg] = val; 1222680SN/A return; 1231070SN/A } 1241070SN/A} 1251917SN/A 1262683Sktlim@umich.eduvoid 127180SN/AISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, 128180SN/A ThreadID tid) 1291858SN/A{ 1302235SN/A switch (misc_reg) { 131180SN/A case MISCREG_FPCR: 1322235SN/A fpcr = val; 133180SN/A return; 134180SN/A case MISCREG_UNIQ: 1352862Sktlim@umich.edu uniq = val; 1362862Sktlim@umich.edu return; 1372313SN/A case MISCREG_LOCKFLAG: 1382313SN/A lock_flag = val; 1392680SN/A return; 1402313SN/A case MISCREG_LOCKADDR: 1412680SN/A lock_addr = val; 1422313SN/A return; 1432313SN/A case MISCREG_INTR: 1442680SN/A intr_flag = val; 1452313SN/A return; 1462361SN/A default: 1473548Sgblack@eecs.umich.edu setIpr(misc_reg, val, tc); 1482361SN/A return; 1492361SN/A } 1502361SN/A} 1512235SN/A 152180SN/A} 153180SN/A