ipr.cc revision 3457
13457Sgblack@eecs.umich.edu/* 23457Sgblack@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 33457Sgblack@eecs.umich.edu * All rights reserved. 43457Sgblack@eecs.umich.edu * 53457Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63457Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73457Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83457Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93457Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103457Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113457Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123457Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133457Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143457Sgblack@eecs.umich.edu * this software without specific prior written permission. 153457Sgblack@eecs.umich.edu * 163457Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173457Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183457Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193457Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203457Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213457Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223457Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233457Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243457Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253457Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263457Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273457Sgblack@eecs.umich.edu * 283457Sgblack@eecs.umich.edu * Authors: Gabe Black 293457Sgblack@eecs.umich.edu */ 303457Sgblack@eecs.umich.edu 313457Sgblack@eecs.umich.edu#include <assert.h> 323457Sgblack@eecs.umich.edu#include <string.h> 333457Sgblack@eecs.umich.edu 343457Sgblack@eecs.umich.edu#include "arch/alpha/ipr.hh" 353457Sgblack@eecs.umich.edu 363457Sgblack@eecs.umich.edunamespace AlphaISA 373457Sgblack@eecs.umich.edu{ 383457Sgblack@eecs.umich.edu md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs] = 393457Sgblack@eecs.umich.edu { 403457Sgblack@eecs.umich.edu //Write only 413457Sgblack@eecs.umich.edu IPR_HWINT_CLR, // H/W interrupt clear register 423457Sgblack@eecs.umich.edu IPR_SL_XMIT, // serial line transmit register 433457Sgblack@eecs.umich.edu IPR_DC_FLUSH, 443457Sgblack@eecs.umich.edu IPR_IC_FLUSH, // instruction cache flush control 453457Sgblack@eecs.umich.edu IPR_ALT_MODE, // alternate mode register 463457Sgblack@eecs.umich.edu IPR_DTB_IA, // DTLB invalidate all register 473457Sgblack@eecs.umich.edu IPR_DTB_IAP, // DTLB invalidate all process register 483457Sgblack@eecs.umich.edu IPR_ITB_IA, // ITLB invalidate all register 493457Sgblack@eecs.umich.edu IPR_ITB_IAP, // ITLB invalidate all process register 503457Sgblack@eecs.umich.edu 513457Sgblack@eecs.umich.edu //Read only 523457Sgblack@eecs.umich.edu IPR_INTID, // interrupt ID register 533457Sgblack@eecs.umich.edu IPR_SL_RCV, // serial line receive register 543457Sgblack@eecs.umich.edu IPR_MM_STAT, // data MMU fault status register 553457Sgblack@eecs.umich.edu IPR_ITB_PTE_TEMP, // ITLB page table entry temp register 563457Sgblack@eecs.umich.edu IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register 573457Sgblack@eecs.umich.edu 583457Sgblack@eecs.umich.edu IPR_ISR, // interrupt summary register 593457Sgblack@eecs.umich.edu IPR_ITB_TAG, // ITLB tag register 603457Sgblack@eecs.umich.edu IPR_ITB_PTE, // ITLB page table entry register 613457Sgblack@eecs.umich.edu IPR_ITB_ASN, // ITLB address space register 623457Sgblack@eecs.umich.edu IPR_ITB_IS, // ITLB invalidate select register 633457Sgblack@eecs.umich.edu IPR_SIRR, // software interrupt request register 643457Sgblack@eecs.umich.edu IPR_ASTRR, // asynchronous system trap request register 653457Sgblack@eecs.umich.edu IPR_ASTER, // asynchronous system trap enable register 663457Sgblack@eecs.umich.edu IPR_EXC_ADDR, // exception address register 673457Sgblack@eecs.umich.edu IPR_EXC_SUM, // exception summary register 683457Sgblack@eecs.umich.edu IPR_EXC_MASK, // exception mask register 693457Sgblack@eecs.umich.edu IPR_PAL_BASE, // PAL base address register 703457Sgblack@eecs.umich.edu IPR_ICM, // instruction current mode 713457Sgblack@eecs.umich.edu IPR_IPLR, // interrupt priority level register 723457Sgblack@eecs.umich.edu IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register 733457Sgblack@eecs.umich.edu IPR_IVPTBR, // virtual page table base register 743457Sgblack@eecs.umich.edu IPR_ICSR, // instruction control and status register 753457Sgblack@eecs.umich.edu IPR_IC_PERR_STAT, // inst cache parity error status register 763457Sgblack@eecs.umich.edu IPR_PMCTR, // performance counter register 773457Sgblack@eecs.umich.edu 783457Sgblack@eecs.umich.edu // PAL temporary registers... 793457Sgblack@eecs.umich.edu // register meanings gleaned from osfpal.s source code 803457Sgblack@eecs.umich.edu IPR_PALtemp0, // local scratch 813457Sgblack@eecs.umich.edu IPR_PALtemp1, // local scratch 823457Sgblack@eecs.umich.edu IPR_PALtemp2, // entUna 833457Sgblack@eecs.umich.edu IPR_PALtemp3, // CPU specific impure area pointer 843457Sgblack@eecs.umich.edu IPR_PALtemp4, // memory management temp 853457Sgblack@eecs.umich.edu IPR_PALtemp5, // memory management temp 863457Sgblack@eecs.umich.edu IPR_PALtemp6, // memory management temp 873457Sgblack@eecs.umich.edu IPR_PALtemp7, // entIF 883457Sgblack@eecs.umich.edu IPR_PALtemp8, // intmask 893457Sgblack@eecs.umich.edu IPR_PALtemp9, // entSys 903457Sgblack@eecs.umich.edu IPR_PALtemp10, // ?? 913457Sgblack@eecs.umich.edu IPR_PALtemp11, // entInt 923457Sgblack@eecs.umich.edu IPR_PALtemp12, // entArith 933457Sgblack@eecs.umich.edu IPR_PALtemp13, // reserved for platform specific PAL 943457Sgblack@eecs.umich.edu IPR_PALtemp14, // reserved for platform specific PAL 953457Sgblack@eecs.umich.edu IPR_PALtemp15, // reserved for platform specific PAL 963457Sgblack@eecs.umich.edu IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0> 973457Sgblack@eecs.umich.edu IPR_PALtemp17, // sysval 983457Sgblack@eecs.umich.edu IPR_PALtemp18, // usp 993457Sgblack@eecs.umich.edu IPR_PALtemp19, // ksp 1003457Sgblack@eecs.umich.edu IPR_PALtemp20, // PTBR 1013457Sgblack@eecs.umich.edu IPR_PALtemp21, // entMM 1023457Sgblack@eecs.umich.edu IPR_PALtemp22, // kgp 1033457Sgblack@eecs.umich.edu IPR_PALtemp23, // PCBB 1043457Sgblack@eecs.umich.edu 1053457Sgblack@eecs.umich.edu IPR_DTB_ASN, // DTLB address space number register 1063457Sgblack@eecs.umich.edu IPR_DTB_CM, // DTLB current mode register 1073457Sgblack@eecs.umich.edu IPR_DTB_TAG, // DTLB tag register 1083457Sgblack@eecs.umich.edu IPR_DTB_PTE, // DTLB page table entry register 1093457Sgblack@eecs.umich.edu 1103457Sgblack@eecs.umich.edu IPR_VA, // fault virtual address register 1113457Sgblack@eecs.umich.edu IPR_VA_FORM, // formatted virtual address register 1123457Sgblack@eecs.umich.edu IPR_MVPTBR, // MTU virtual page table base register 1133457Sgblack@eecs.umich.edu IPR_DTB_IS, // DTLB invalidate single register 1143457Sgblack@eecs.umich.edu IPR_CC, // cycle counter register 1153457Sgblack@eecs.umich.edu IPR_CC_CTL, // cycle counter control register 1163457Sgblack@eecs.umich.edu IPR_MCSR, // MTU control register 1173457Sgblack@eecs.umich.edu 1183457Sgblack@eecs.umich.edu IPR_DC_PERR_STAT, // Dcache parity error status register 1193457Sgblack@eecs.umich.edu IPR_DC_TEST_CTL, // Dcache test tag control register 1203457Sgblack@eecs.umich.edu IPR_DC_TEST_TAG, // Dcache test tag register 1213457Sgblack@eecs.umich.edu IPR_DC_TEST_TAG_TEMP, // Dcache test tag temporary register 1223457Sgblack@eecs.umich.edu IPR_DC_MODE, // Dcache mode register 1233457Sgblack@eecs.umich.edu IPR_MAF_MODE // miss address file mode register 1243457Sgblack@eecs.umich.edu }; 1253457Sgblack@eecs.umich.edu 1263457Sgblack@eecs.umich.edu int IprToMiscRegIndex[MaxInternalProcRegs]; 1273457Sgblack@eecs.umich.edu 1283457Sgblack@eecs.umich.edu void initializeIprTable() 1293457Sgblack@eecs.umich.edu { 1303457Sgblack@eecs.umich.edu static bool initialized = false; 1313457Sgblack@eecs.umich.edu if(initialized) 1323457Sgblack@eecs.umich.edu return; 1333457Sgblack@eecs.umich.edu 1343457Sgblack@eecs.umich.edu memset(IprToMiscRegIndex, -1, MaxInternalProcRegs * sizeof(int)); 1353457Sgblack@eecs.umich.edu 1363457Sgblack@eecs.umich.edu for(int x = 0; x < NumInternalProcRegs; x++) 1373457Sgblack@eecs.umich.edu IprToMiscRegIndex[MiscRegIndexToIpr[x]] = x; 1383457Sgblack@eecs.umich.edu } 1393457Sgblack@eecs.umich.edu} 1403457Sgblack@eecs.umich.edu 141