13457Sgblack@eecs.umich.edu/* 23457Sgblack@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 33457Sgblack@eecs.umich.edu * All rights reserved. 43457Sgblack@eecs.umich.edu * 53457Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63457Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73457Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83457Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93457Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103457Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113457Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123457Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133457Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143457Sgblack@eecs.umich.edu * this software without specific prior written permission. 153457Sgblack@eecs.umich.edu * 163457Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173457Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183457Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193457Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203457Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213457Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223457Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233457Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243457Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253457Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263457Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273457Sgblack@eecs.umich.edu * 283457Sgblack@eecs.umich.edu * Authors: Gabe Black 293457Sgblack@eecs.umich.edu */ 303457Sgblack@eecs.umich.edu 3111793Sbrandon.potter@amd.com#include "arch/alpha/ipr.hh" 3211793Sbrandon.potter@amd.com 335569Snate@binkert.org#include <cassert> 345569Snate@binkert.org#include <cstring> 353457Sgblack@eecs.umich.edu 365569Snate@binkert.orgnamespace AlphaISA { 375569Snate@binkert.org 385569Snate@binkert.orgmd_ipr_names MiscRegIndexToIpr[NumInternalProcRegs] = { 395569Snate@binkert.org 405569Snate@binkert.org //Write only 415569Snate@binkert.org RAW_IPR_HWINT_CLR, // H/W interrupt clear register 425569Snate@binkert.org RAW_IPR_SL_XMIT, // serial line transmit register 435569Snate@binkert.org RAW_IPR_DC_FLUSH, 445569Snate@binkert.org RAW_IPR_IC_FLUSH, // instruction cache flush control 455569Snate@binkert.org RAW_IPR_ALT_MODE, // alternate mode register 465569Snate@binkert.org RAW_IPR_DTB_IA, // DTLB invalidate all register 475569Snate@binkert.org RAW_IPR_DTB_IAP, // DTLB invalidate all process register 485569Snate@binkert.org RAW_IPR_ITB_IA, // ITLB invalidate all register 495569Snate@binkert.org RAW_IPR_ITB_IAP, // ITLB invalidate all process register 505569Snate@binkert.org 515569Snate@binkert.org //Read only 525569Snate@binkert.org RAW_IPR_INTID, // interrupt ID register 535569Snate@binkert.org RAW_IPR_SL_RCV, // serial line receive register 545569Snate@binkert.org RAW_IPR_MM_STAT, // data MMU fault status register 555569Snate@binkert.org RAW_IPR_ITB_PTE_TEMP, // ITLB page table entry temp register 565569Snate@binkert.org RAW_IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register 575569Snate@binkert.org 585569Snate@binkert.org RAW_IPR_ISR, // interrupt summary register 595569Snate@binkert.org RAW_IPR_ITB_TAG, // ITLB tag register 605569Snate@binkert.org RAW_IPR_ITB_PTE, // ITLB page table entry register 615569Snate@binkert.org RAW_IPR_ITB_ASN, // ITLB address space register 625569Snate@binkert.org RAW_IPR_ITB_IS, // ITLB invalidate select register 635569Snate@binkert.org RAW_IPR_SIRR, // software interrupt request register 645569Snate@binkert.org RAW_IPR_ASTRR, // asynchronous system trap request register 655569Snate@binkert.org RAW_IPR_ASTER, // asynchronous system trap enable register 665569Snate@binkert.org RAW_IPR_EXC_ADDR, // exception address register 675569Snate@binkert.org RAW_IPR_EXC_SUM, // exception summary register 685569Snate@binkert.org RAW_IPR_EXC_MASK, // exception mask register 695569Snate@binkert.org RAW_IPR_PAL_BASE, // PAL base address register 705569Snate@binkert.org RAW_IPR_ICM, // instruction current mode 715569Snate@binkert.org RAW_IPR_IPLR, // interrupt priority level register 725569Snate@binkert.org RAW_IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register 735569Snate@binkert.org RAW_IPR_IVPTBR, // virtual page table base register 745569Snate@binkert.org RAW_IPR_ICSR, // instruction control and status register 755569Snate@binkert.org RAW_IPR_IC_PERR_STAT, // inst cache parity error status register 765569Snate@binkert.org RAW_IPR_PMCTR, // performance counter register 775569Snate@binkert.org 785569Snate@binkert.org // PAL temporary registers... 795569Snate@binkert.org // register meanings gleaned from osfpal.s source code 805569Snate@binkert.org RAW_IPR_PALtemp0, // local scratch 815569Snate@binkert.org RAW_IPR_PALtemp1, // local scratch 825569Snate@binkert.org RAW_IPR_PALtemp2, // entUna 835569Snate@binkert.org RAW_IPR_PALtemp3, // CPU specific impure area pointer 845569Snate@binkert.org RAW_IPR_PALtemp4, // memory management temp 855569Snate@binkert.org RAW_IPR_PALtemp5, // memory management temp 865569Snate@binkert.org RAW_IPR_PALtemp6, // memory management temp 875569Snate@binkert.org RAW_IPR_PALtemp7, // entIF 885569Snate@binkert.org RAW_IPR_PALtemp8, // intmask 895569Snate@binkert.org RAW_IPR_PALtemp9, // entSys 905569Snate@binkert.org RAW_IPR_PALtemp10, // ?? 915569Snate@binkert.org RAW_IPR_PALtemp11, // entInt 925569Snate@binkert.org RAW_IPR_PALtemp12, // entArith 935569Snate@binkert.org RAW_IPR_PALtemp13, // reserved for platform specific PAL 945569Snate@binkert.org RAW_IPR_PALtemp14, // reserved for platform specific PAL 955569Snate@binkert.org RAW_IPR_PALtemp15, // reserved for platform specific PAL 965569Snate@binkert.org RAW_IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0> 975569Snate@binkert.org RAW_IPR_PALtemp17, // sysval 985569Snate@binkert.org RAW_IPR_PALtemp18, // usp 995569Snate@binkert.org RAW_IPR_PALtemp19, // ksp 1005569Snate@binkert.org RAW_IPR_PALtemp20, // PTBR 1015569Snate@binkert.org RAW_IPR_PALtemp21, // entMM 1025569Snate@binkert.org RAW_IPR_PALtemp22, // kgp 1035569Snate@binkert.org RAW_IPR_PALtemp23, // PCBB 1045569Snate@binkert.org 1055569Snate@binkert.org RAW_IPR_DTB_ASN, // DTLB address space number register 1065569Snate@binkert.org RAW_IPR_DTB_CM, // DTLB current mode register 1075569Snate@binkert.org RAW_IPR_DTB_TAG, // DTLB tag register 1085569Snate@binkert.org RAW_IPR_DTB_PTE, // DTLB page table entry register 1095569Snate@binkert.org 1105569Snate@binkert.org RAW_IPR_VA, // fault virtual address register 1115569Snate@binkert.org RAW_IPR_VA_FORM, // formatted virtual address register 1125569Snate@binkert.org RAW_IPR_MVPTBR, // MTU virtual page table base register 1135569Snate@binkert.org RAW_IPR_DTB_IS, // DTLB invalidate single register 1145569Snate@binkert.org RAW_IPR_CC, // cycle counter register 1155569Snate@binkert.org RAW_IPR_CC_CTL, // cycle counter control register 1165569Snate@binkert.org RAW_IPR_MCSR, // MTU control register 1175569Snate@binkert.org 1185569Snate@binkert.org RAW_IPR_DC_PERR_STAT, // Dcache parity error status register 1195569Snate@binkert.org RAW_IPR_DC_TEST_CTL, // Dcache test tag control register 1205569Snate@binkert.org RAW_IPR_DC_TEST_TAG, // Dcache test tag register 1215569Snate@binkert.org RAW_IPR_DC_TEST_TAG_TEMP, // Dcache test tag temporary register 1225569Snate@binkert.org RAW_IPR_DC_MODE, // Dcache mode register 1235569Snate@binkert.org RAW_IPR_MAF_MODE // miss address file mode register 1245569Snate@binkert.org}; 1255569Snate@binkert.org 1265569Snate@binkert.orgint IprToMiscRegIndex[MaxInternalProcRegs]; 1275569Snate@binkert.org 1285569Snate@binkert.orgvoid 1295569Snate@binkert.orginitializeIprTable() 1303457Sgblack@eecs.umich.edu{ 1315569Snate@binkert.org static bool initialized = false; 1325569Snate@binkert.org if (initialized) 1335569Snate@binkert.org return; 1343457Sgblack@eecs.umich.edu 1355569Snate@binkert.org memset(IprToMiscRegIndex, -1, MaxInternalProcRegs * sizeof(int)); 1363457Sgblack@eecs.umich.edu 1375569Snate@binkert.org for (int x = 0; x < NumInternalProcRegs; x++) 1385569Snate@binkert.org IprToMiscRegIndex[MiscRegIndexToIpr[x]] = x; 1393457Sgblack@eecs.umich.edu} 1403457Sgblack@eecs.umich.edu 1415569Snate@binkert.org} // namespace AlphaISA 1425569Snate@binkert.org 143