interrupts.hh revision 5647:b06b49498c79 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Kevin Lim
30 */
31
32#ifndef __ARCH_ALPHA_INTERRUPT_HH__
33#define __ARCH_ALPHA_INTERRUPT_HH__
34
35#include "arch/alpha/faults.hh"
36#include "arch/alpha/isa_traits.hh"
37#include "base/compiler.hh"
38#include "base/trace.hh"
39#include "cpu/thread_context.hh"
40#include "params/AlphaInterrupts.hh"
41#include "sim/sim_object.hh"
42
43namespace AlphaISA {
44
45class Interrupts : public SimObject
46{
47  private:
48    bool newInfoSet;
49    int newIpl;
50    int newSummary;
51
52  protected:
53    uint64_t interrupts[NumInterruptLevels];
54    uint64_t intstatus;
55
56  public:
57    typedef AlphaInterruptsParams Params;
58
59    const Params *
60    params() const
61    {
62        return dynamic_cast<const Params *>(_params);
63    }
64
65    Interrupts(Params * p) : SimObject(p)
66    {
67        memset(interrupts, 0, sizeof(interrupts));
68        intstatus = 0;
69        newInfoSet = false;
70    }
71
72    void
73    post(int int_num, int index)
74    {
75        DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
76
77        if (int_num < 0 || int_num >= NumInterruptLevels)
78            panic("int_num out of bounds\n");
79
80        if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
81            panic("int_num out of bounds\n");
82
83        interrupts[int_num] |= 1 << index;
84        intstatus |= (ULL(1) << int_num);
85    }
86
87    void
88    clear(int int_num, int index)
89    {
90        DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
91
92        if (int_num < 0 || int_num >= NumInterruptLevels)
93            panic("int_num out of bounds\n");
94
95        if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
96            panic("int_num out of bounds\n");
97
98        interrupts[int_num] &= ~(1 << index);
99        if (interrupts[int_num] == 0)
100            intstatus &= ~(ULL(1) << int_num);
101    }
102
103    void
104    clear_all()
105    {
106        DPRINTF(Interrupt, "Interrupts all cleared\n");
107
108        memset(interrupts, 0, sizeof(interrupts));
109        intstatus = 0;
110    }
111
112    void
113    serialize(std::ostream &os)
114    {
115        SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
116        SERIALIZE_SCALAR(intstatus);
117    }
118
119    void
120    unserialize(Checkpoint *cp, const std::string &section)
121    {
122        UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
123        UNSERIALIZE_SCALAR(intstatus);
124    }
125
126    bool
127    check_interrupts(ThreadContext *tc) const
128    {
129        return (intstatus != 0) && !(tc->readPC() & 0x3);
130    }
131
132    Fault
133    getInterrupt(ThreadContext *tc)
134    {
135        int ipl = 0;
136        int summary = 0;
137
138        if (tc->readMiscRegNoEffect(IPR_ASTRR))
139            panic("asynchronous traps not implemented\n");
140
141        if (tc->readMiscRegNoEffect(IPR_SIRR)) {
142            for (int i = INTLEVEL_SOFTWARE_MIN;
143                 i < INTLEVEL_SOFTWARE_MAX; i++) {
144                if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
145                    // See table 4-19 of 21164 hardware reference
146                    ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
147                    summary |= (ULL(1) << i);
148                }
149            }
150        }
151
152        uint64_t interrupts = intstatus;
153        if (interrupts) {
154            for (int i = INTLEVEL_EXTERNAL_MIN;
155                 i < INTLEVEL_EXTERNAL_MAX; i++) {
156                if (interrupts & (ULL(1) << i)) {
157                    // See table 4-19 of 21164 hardware reference
158                    ipl = i;
159                    summary |= (ULL(1) << i);
160                }
161            }
162        }
163
164        if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
165            newIpl = ipl;
166            newSummary = summary;
167            newInfoSet = true;
168            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
169                    tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
170
171            return new InterruptFault;
172        } else {
173            return NoFault;
174        }
175    }
176
177    void
178    updateIntrInfo(ThreadContext *tc)
179    {
180        assert(newInfoSet);
181        tc->setMiscRegNoEffect(IPR_ISR, newSummary);
182        tc->setMiscRegNoEffect(IPR_INTID, newIpl);
183        newInfoSet = false;
184    }
185};
186
187} // namespace AlphaISA
188
189#endif // __ARCH_ALPHA_INTERRUPT_HH__
190
191