interrupts.hh revision 4172:141705d83494 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Kevin Lim
30 */
31
32#ifndef __ARCH_ALPHA_INTERRUPT_HH__
33#define __ARCH_ALPHA_INTERRUPT_HH__
34
35#include "arch/alpha/faults.hh"
36#include "arch/alpha/isa_traits.hh"
37#include "base/compiler.hh"
38#include "cpu/thread_context.hh"
39
40namespace AlphaISA
41{
42    class Interrupts
43    {
44      protected:
45        uint64_t interrupts[NumInterruptLevels];
46        uint64_t intstatus;
47
48      public:
49        Interrupts()
50        {
51            memset(interrupts, 0, sizeof(interrupts));
52            intstatus = 0;
53            newInfoSet = false;
54        }
55
56        void post(int int_num, int index)
57        {
58            DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
59
60            if (int_num < 0 || int_num >= NumInterruptLevels)
61                panic("int_num out of bounds\n");
62
63            if (index < 0 || index >= sizeof(uint64_t) * 8)
64                panic("int_num out of bounds\n");
65
66            interrupts[int_num] |= 1 << index;
67            intstatus |= (ULL(1) << int_num);
68        }
69
70        void clear(int int_num, int index)
71        {
72            DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
73
74            if (int_num < 0 || int_num >= TheISA::NumInterruptLevels)
75                panic("int_num out of bounds\n");
76
77            if (index < 0 || index >= sizeof(uint64_t) * 8)
78                panic("int_num out of bounds\n");
79
80            interrupts[int_num] &= ~(1 << index);
81            if (interrupts[int_num] == 0)
82                intstatus &= ~(ULL(1) << int_num);
83        }
84
85        void clear_all()
86        {
87            DPRINTF(Interrupt, "Interrupts all cleared\n");
88
89            memset(interrupts, 0, sizeof(interrupts));
90            intstatus = 0;
91        }
92
93        void serialize(std::ostream &os)
94        {
95            SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
96            SERIALIZE_SCALAR(intstatus);
97        }
98
99        void unserialize(Checkpoint *cp, const std::string &section)
100        {
101            UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
102            UNSERIALIZE_SCALAR(intstatus);
103        }
104
105        bool check_interrupts(ThreadContext * tc) const
106        {
107            return (intstatus != 0) && !(tc->readPC() & 0x3);
108        }
109
110        Fault getInterrupt(ThreadContext * tc)
111        {
112            int ipl = 0;
113            int summary = 0;
114
115            if (tc->readMiscRegNoEffect(IPR_ASTRR))
116                panic("asynchronous traps not implemented\n");
117
118            if (tc->readMiscRegNoEffect(IPR_SIRR)) {
119                for (int i = INTLEVEL_SOFTWARE_MIN;
120                     i < INTLEVEL_SOFTWARE_MAX; i++) {
121                    if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
122                        // See table 4-19 of 21164 hardware reference
123                        ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
124                        summary |= (ULL(1) << i);
125                    }
126                }
127            }
128
129            uint64_t interrupts = intstatus;
130            if (interrupts) {
131                for (int i = INTLEVEL_EXTERNAL_MIN;
132                    i < INTLEVEL_EXTERNAL_MAX; i++) {
133                    if (interrupts & (ULL(1) << i)) {
134                        // See table 4-19 of 21164 hardware reference
135                        ipl = i;
136                        summary |= (ULL(1) << i);
137                    }
138                }
139            }
140
141            if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
142                newIpl = ipl;
143                newSummary = summary;
144                newInfoSet = true;
145                DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
146                        tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
147
148                return new InterruptFault;
149            } else {
150                return NoFault;
151            }
152        }
153
154        void updateIntrInfo(ThreadContext *tc)
155        {
156            assert(newInfoSet);
157            tc->setMiscRegNoEffect(IPR_ISR, newSummary);
158            tc->setMiscRegNoEffect(IPR_INTID, newIpl);
159            newInfoSet = false;
160        }
161
162        uint64_t get_vec(int int_num)
163        {
164            panic("Shouldn't be called for Alpha\n");
165            M5_DUMMY_RETURN
166        }
167
168      private:
169        bool newInfoSet;
170        int newIpl;
171        int newSummary;
172    };
173}
174
175#endif
176
177